mirror of https://github.com/YosysHQ/yosys.git
Redesign of cell cost API
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
8110fb9266
commit
100c377451
158
kernel/cost.h
158
kernel/cost.h
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@ -24,86 +24,92 @@
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YOSYS_NAMESPACE_BEGIN
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int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false);
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inline int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL::Const> ¶meters = dict<RTLIL::IdString, RTLIL::Const>(),
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RTLIL::Design *design = nullptr, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false)
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struct CellCosts
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{
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static dict<RTLIL::IdString, int> gate_cost = {
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{ "$_BUF_", 1 },
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{ "$_NOT_", 2 },
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{ "$_AND_", 4 },
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{ "$_NAND_", 4 },
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{ "$_OR_", 4 },
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{ "$_NOR_", 4 },
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{ "$_ANDNOT_", 4 },
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{ "$_ORNOT_", 4 },
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{ "$_XOR_", 8 },
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{ "$_XNOR_", 8 },
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{ "$_AOI3_", 6 },
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{ "$_OAI3_", 6 },
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{ "$_AOI4_", 8 },
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{ "$_OAI4_", 8 },
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{ "$_MUX_", 4 },
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{ "$_NMUX_", 4 }
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};
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// match costs in "stat -tech cmos"
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static dict<RTLIL::IdString, int> cmos_gate_cost = {
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{ "$_BUF_", 1 },
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{ "$_NOT_", 2 },
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{ "$_AND_", 6 },
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{ "$_NAND_", 4 },
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{ "$_OR_", 6 },
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{ "$_NOR_", 4 },
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{ "$_ANDNOT_", 6 },
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{ "$_ORNOT_", 6 },
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{ "$_XOR_", 12 },
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{ "$_XNOR_", 12 },
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{ "$_AOI3_", 6 },
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{ "$_OAI3_", 6 },
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{ "$_AOI4_", 8 },
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{ "$_OAI4_", 8 },
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{ "$_MUX_", 12 },
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{ "$_NMUX_", 10 }
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};
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if (cmos_cost && cmos_gate_cost.count(type))
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return cmos_gate_cost.at(type);
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if (gate_cost.count(type))
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return gate_cost.at(type);
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if (parameters.empty() && design && design->module(type))
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{
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RTLIL::Module *mod = design->module(type);
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if (mod->attributes.count("\\cost"))
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return mod->attributes.at("\\cost").as_int();
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dict<RTLIL::IdString, int> local_mod_cost_cache;
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if (mod_cost_cache == nullptr)
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mod_cost_cache = &local_mod_cost_cache;
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if (mod_cost_cache->count(mod->name))
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return mod_cost_cache->at(mod->name);
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int module_cost = 1;
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for (auto c : mod->cells())
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module_cost += get_cell_cost(c, mod_cost_cache);
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(*mod_cost_cache)[mod->name] = module_cost;
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return module_cost;
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static const dict<RTLIL::IdString, int>& default_gate_cost() {
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static const dict<RTLIL::IdString, int> db = {
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{ "$_BUF_", 1 },
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{ "$_NOT_", 2 },
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{ "$_AND_", 4 },
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{ "$_NAND_", 4 },
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{ "$_OR_", 4 },
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{ "$_NOR_", 4 },
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{ "$_ANDNOT_", 4 },
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{ "$_ORNOT_", 4 },
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{ "$_XOR_", 6 },
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{ "$_XNOR_", 6 },
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{ "$_AOI3_", 6 },
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{ "$_OAI3_", 6 },
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{ "$_AOI4_", 8 },
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{ "$_OAI4_", 8 },
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{ "$_MUX_", 4 },
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{ "$_NMUX_", 4 }
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};
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return db;
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}
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log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
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return 1;
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}
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static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
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static const dict<RTLIL::IdString, int> db = {
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{ "$_BUF_", 1 },
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{ "$_NOT_", 2 },
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{ "$_AND_", 6 },
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{ "$_NAND_", 4 },
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{ "$_OR_", 6 },
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{ "$_NOR_", 4 },
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{ "$_ANDNOT_", 6 },
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{ "$_ORNOT_", 6 },
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{ "$_XOR_", 12 },
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{ "$_XNOR_", 12 },
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{ "$_AOI3_", 6 },
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{ "$_OAI3_", 6 },
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{ "$_AOI4_", 8 },
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{ "$_OAI4_", 8 },
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{ "$_MUX_", 12 },
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{ "$_NMUX_", 10 }
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};
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return db;
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}
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inline int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache, bool cmos_cost)
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{
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return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache, cmos_cost);
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}
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dict<RTLIL::IdString, int> mod_cost_cache;
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const dict<RTLIL::IdString, int> *gate_cost = nullptr;
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Design *design = nullptr;
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int get(RTLIL::IdString type) const
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{
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if (gate_cost && gate_cost->count(type))
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return gate_cost->at(type);
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log_warning("Can't determine cost of %s cell.\n", log_id(type));
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return 1;
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}
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int get(RTLIL::Cell *cell)
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{
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if (gate_cost && gate_cost->count(cell->type))
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return gate_cost->at(cell->type);
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if (design && design->module(cell->type) && cell->parameters.empty())
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{
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RTLIL::Module *mod = design->module(cell->type);
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if (mod->attributes.count("\\cost"))
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return mod->attributes.at("\\cost").as_int();
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if (mod_cost_cache.count(mod->name))
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return mod_cost_cache.at(mod->name);
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int module_cost = 1;
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for (auto c : mod->cells())
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module_cost += get(c);
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mod_cost_cache[mod->name] = module_cost;
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return module_cost;
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}
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log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
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return 1;
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}
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};
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YOSYS_NAMESPACE_END
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@ -931,9 +931,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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{
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log_header(design, "Executing ABC.\n");
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auto cell_cost = [](IdString cell_type) {
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return get_cell_cost(cell_type, dict<RTLIL::IdString, RTLIL::Const>(), nullptr, nullptr, cmos_cost);
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};
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auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
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buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
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f = fopen(buffer.c_str(), "wt");
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@ -941,42 +939,42 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
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fprintf(f, "GATE ONE 1 Y=CONST1;\n");
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fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost("$_BUF_"));
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fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost("$_NOT_"));
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fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_BUF_"));
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fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOT_"));
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if (enabled_gates.empty() || enabled_gates.count("AND"))
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fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost("$_AND_"));
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fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_AND_"));
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if (enabled_gates.empty() || enabled_gates.count("NAND"))
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fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_NAND_"));
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fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NAND_"));
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if (enabled_gates.empty() || enabled_gates.count("OR"))
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fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost("$_OR_"));
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fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_OR_"));
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if (enabled_gates.empty() || enabled_gates.count("NOR"))
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fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_NOR_"));
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fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOR_"));
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if (enabled_gates.empty() || enabled_gates.count("XOR"))
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fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_XOR_"));
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fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XOR_"));
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if (enabled_gates.empty() || enabled_gates.count("XNOR"))
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fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_XNOR_"));
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fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XNOR_"));
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if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
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fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_ANDNOT_"));
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fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ANDNOT_"));
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if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
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fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_ORNOT_"));
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fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ORNOT_"));
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if (enabled_gates.empty() || enabled_gates.count("AOI3"))
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fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_AOI3_"));
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fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI3_"));
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if (enabled_gates.empty() || enabled_gates.count("OAI3"))
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fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_OAI3_"));
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fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI3_"));
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if (enabled_gates.empty() || enabled_gates.count("AOI4"))
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fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_AOI4_"));
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fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI4_"));
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if (enabled_gates.empty() || enabled_gates.count("OAI4"))
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fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_OAI4_"));
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fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI4_"));
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if (enabled_gates.empty() || enabled_gates.count("MUX"))
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fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_MUX_"));
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fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_MUX_"));
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if (enabled_gates.empty() || enabled_gates.count("NMUX"))
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fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_NMUX_"));
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fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_NMUX_"));
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if (map_mux4)
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fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost("$_MUX_"));
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fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at("$_MUX_"));
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if (map_mux8)
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fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost("$_MUX_"));
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fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at("$_MUX_"));
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if (map_mux16)
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fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost("$_MUX_"));
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fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at("$_MUX_"));
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fclose(f);
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if (!lut_costs.empty()) {
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