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move attributes to wires

This commit is contained in:
Marcin Kościelnicki 2019-08-13 19:36:59 +00:00
parent 49765ec19e
commit 3c75a72feb
8 changed files with 555 additions and 320 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
passes/techmap/clkbufmap.cc
View File

@ -112,27 +112,13 @@ struct ClkbufmapPass : public Pass {
for (auto module : modules_sorted)
{
if (module->get_blackbox_attribute()) {
auto it = module->attributes.find("\\clkbuf_driver");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split_tokens(value, ",")) {
auto wire = module->wire(RTLIL::escape_id(name));
if (!wire)
log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
for (auto wire : module->wires()) {
if (wire->get_bool_attribute("\\clkbuf_driver"))
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
}
}
it = module->attributes.find("\\clkbuf_sink");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split_tokens(value, ",")) {
auto wire = module->wire(RTLIL::escape_id(name));
if (!wire)
log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
if (wire->get_bool_attribute("\\clkbuf_sink"))
for (int i = 0; i < GetSize(wire); i++)
sink_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
}
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
}
continue;
}

13
passes/techmap/iopadmap.cc
View File

@ -173,15 +173,10 @@ struct IopadmapPass : public Pass {
ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4)));
for (auto module : design->modules())
{
auto it = module->attributes.find("\\iopad_external_pin");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split_tokens(value, ",")) {
ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
}
}
}
if (module->get_blackbox_attribute())
for (auto wire : module->wires())
if (wire->get_bool_attribute("\\iopad_external_pin"))
ignore.insert(make_pair(module->name, wire->name));
for (auto module : design->selected_modules())
{

75
techlibs/xilinx/cells_sim.v
View File

@ -29,26 +29,35 @@ module GND(output G);
assign G = 0;
endmodule
module IBUF(output O, input I);
module IBUF(
output O,
(* iopad_external_pin *)
input I);
parameter IOSTANDARD = "default";
parameter IBUF_LOW_PWR = 0;
assign O = I;
endmodule
module OBUF(output O, input I);
module OBUF(
(* iopad_external_pin *)
output O,
input I);
parameter IOSTANDARD = "default";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
assign O = I;
endmodule
(* clkbuf_driver = "O" *)
module BUFG(output O, input I);
module BUFG(
(* clkbuf_driver *)
output O,
input I);
assign O = I;
endmodule
(* clkbuf_driver = "O" *)
module BUFGCTRL(
(* clkbuf_driver *)
output O,
input I0, input I1,
input S0, input S1,
@ -74,8 +83,11 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
endmodule
(* clkbuf_driver = "O" *)
module BUFHCE(output O, input I, input CE);
module BUFHCE(
(* clkbuf_driver *)
output O,
input I,
input CE);
parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
@ -216,8 +228,7 @@ endmodule
`endif
(* clkbuf_sink = "C" *)
module FDRE (output reg Q, input C, CE, D, R);
module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -229,8 +240,7 @@ module FDRE (output reg Q, input C, CE, D, R);
endcase endgenerate
endmodule
(* clkbuf_sink = "C" *)
module FDSE (output reg Q, input C, CE, D, S);
module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -242,8 +252,7 @@ module FDSE (output reg Q, input C, CE, D, S);
endcase endgenerate
endmodule
(* clkbuf_sink = "C" *)
module FDCE (output reg Q, input C, CE, D, CLR);
module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -257,8 +266,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
endcase endgenerate
endmodule
(* clkbuf_sink = "C" *)
module FDPE (output reg Q, input C, CE, D, PRE);
module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -272,39 +280,36 @@ module FDPE (output reg Q, input C, CE, D, PRE);
endcase endgenerate
endmodule
(* clkbuf_sink = "C" *)
module FDRE_1 (output reg Q, input C, CE, D, R);
module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
(* clkbuf_sink = "C" *)
module FDSE_1 (output reg Q, input C, CE, D, S);
module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
(* clkbuf_sink = "C" *)
module FDCE_1 (output reg Q, input C, CE, D, CLR);
module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
(* clkbuf_sink = "C" *)
module FDPE_1 (output reg Q, input C, CE, D, PRE);
module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
(* clkbuf_sink = "WCLK" *)
(* abc_box_id = 5, abc_scc_break="D,WE" *)
module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
(* clkbuf_sink *)
input WCLK,
input D, WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@ -319,11 +324,12 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* clkbuf_sink = "WCLK" *)
(* abc_box_id = 6, abc_scc_break="D,WE" *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
(* clkbuf_sink *)
input WCLK,
input D, WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@ -338,11 +344,12 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* clkbuf_sink = "WCLK" *)
(* abc_box_id = 7, abc_scc_break="D,WE" *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input D, WE,
(* clkbuf_sink *)
input WCLK,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;
@ -354,10 +361,11 @@ module RAM128X1D (
always @(posedge clk) if (WE) mem[A] <= D;
endmodule
(* clkbuf_sink = "CLK" *)
module SRL16E (
output Q,
input A0, A1, A2, A3, CE, CLK, D
(* clkbuf_sink *)
input CLK,
input A0, A1, A2, A3, CE, D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
@ -373,12 +381,13 @@ module SRL16E (
endgenerate
endmodule
(* clkbuf_sink = "CLK" *)
module SRLC32E (
output Q,
output Q31,
input [4:0] A,
input CE, CLK, D
(* clkbuf_sink *)
input CLK,
input CE, D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;

257
techlibs/xilinx/cells_xtra.py Normal file
View File

@ -0,0 +1,257 @@
#!/usr/bin/env python3
from argparse import ArgumentParser
from io import StringIO
from enum import Enum, auto
import os.path
import sys
class Cell:
def __init__(self, name, keep=False, port_attrs={}):
self.name = name
self.keep = keep
self.port_attrs = port_attrs
CELLS = [
# Design elements types listed in Xilinx UG953
Cell('BSCANE2', keep=True),
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
#Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
Cell('CAPTUREE2', keep=True),
# Cell('CARRY4'),
Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
Cell('DCIRESET', keep=True),
Cell('DNA_PORT'),
Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
Cell('EFUSE_USR'),
# Cell('FDCE'),
# Cell('FDPE'),
# Cell('FDRE'),
# Cell('FDSE'),
Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
Cell('FRAME_ECCE2'),
Cell('GTHE2_CHANNEL'),
Cell('GTHE2_COMMON'),
Cell('GTPE2_CHANNEL'),
Cell('GTPE2_COMMON'),
Cell('GTXE2_CHANNEL'),
Cell('GTXE2_COMMON'),
# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('ICAPE2', keep=True),
Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
Cell('ISERDESE2', port_attrs={
'CLK': ['clkbuf_sink'],
'CLKB': ['clkbuf_sink'],
'OCLK': ['clkbuf_sink'],
'OCLKB': ['clkbuf_sink'],
'CLKDIV': ['clkbuf_sink'],
'CLKDIVP': ['clkbuf_sink'],
}),
Cell('KEEPER'),
Cell('LDCE'),
Cell('LDPE'),
# Cell('LUT1'),
# Cell('LUT2'),
# Cell('LUT3'),
# Cell('LUT4'),
# Cell('LUT5'),
# Cell('LUT6'),
#Cell('LUT6_2'),
Cell('MMCME2_ADV'),
Cell('MMCME2_BASE'),
# Cell('MUXF7'),
# Cell('MUXF8'),
# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
Cell('PHASER_IN'),
Cell('PHASER_IN_PHY'),
Cell('PHASER_OUT'),
Cell('PHASER_OUT_PHY'),
Cell('PHASER_REF'),
Cell('PHY_CONTROL'),
Cell('PLLE2_ADV'),
Cell('PLLE2_BASE'),
Cell('PS7', keep=True),
Cell('PULLDOWN'),
Cell('PULLUP'),
#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
# Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
# Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
Cell('ROM128X1'),
Cell('ROM256X1'),
Cell('ROM32X1'),
Cell('ROM64X1'),
#Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
#Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
Cell('STARTUPE2', keep=True),
Cell('USR_ACCESSE2'),
Cell('XADC'),
]
class State(Enum):
OUTSIDE = auto()
IN_MODULE = auto()
IN_OTHER_MODULE = auto()
IN_FUNCTION = auto()
IN_TASK = auto()
def xtract_cell_decl(cell, dirs, outf):
for dir in dirs:
fname = os.path.join(dir, cell.name + '.v')
try:
with open(fname) as f:
state = State.OUTSIDE
found = False
# Probably the most horrible Verilog "parser" ever written.
for l in f:
l = l.partition('//')[0]
l = l.strip()
if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
if found:
print('Multiple modules in {}.'.format(fname))
sys.exit(1)
elif state != State.OUTSIDE:
print('Nested modules in {}.'.format(fname))
sys.exit(1)
found = True
state = State.IN_MODULE
if cell.keep:
outf.write('(* keep *)\n')
outf.write('module {} (...);\n'.format(cell.name))
elif l.startswith('module '):
if state != State.OUTSIDE:
print('Nested modules in {}.'.format(fname))
sys.exit(1)
state = State.IN_OTHER_MODULE
elif l.startswith('task '):
if state == State.IN_MODULE:
state = State.IN_TASK
elif l.startswith('function '):
if state == State.IN_MODULE:
state = State.IN_FUNCTION
elif l == 'endtask':
if state == State.IN_TASK:
state = State.IN_MODULE
elif l == 'endfunction':
if state == State.IN_FUNCTION:
state = State.IN_MODULE
elif l == 'endmodule':
if state == State.IN_MODULE:
outf.write(l + '\n')
outf.write('\n')
elif state != State.IN_OTHER_MODULE:
print('endmodule in weird place in {}.'.format(cell.name, fname))
sys.exit(1)
state = State.OUTSIDE
elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
if l.endswith((';', ',')):
l = l[:-1]
if ';' in l:
print('Weird port line in {} [{}].'.format(fname, l))
sys.exit(1)
kind, _, ports = l.partition(' ')
for port in ports.split(','):
port = port.strip()
for attr in cell.port_attrs.get(port, []):
outf.write(' (* {} *)\n'.format(attr))
outf.write(' {} {};\n'.format(kind, port))
elif l.startswith('parameter ') and state == State.IN_MODULE:
if 'UNPLACED' in l:
continue
if l.endswith((';', ',')):
l = l[:-1]
while ' ' in l:
l = l.replace(' ', ' ')
if ';' in l:
print('Weird parameter line in {} [{}].'.format(fname, l))
sys.exit(1)
outf.write(' {};\n'.format(l))
if state != State.OUTSIDE:
print('endmodule not found in {}.'.format(fname))
sys.exit(1)
if not found:
print('Cannot find module {} in {}.'.format(cell.name, fname))
sys.exit(1)
return
except FileNotFoundError:
continue
print('Cannot find {}.'.format(cell.name))
sys.exit(1)
if __name__ == '__main__':
parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from Vivado.')
parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
args = parser.parse_args()
dirs = [
os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
]
for dir in dirs:
if not os.path.isdir(dir):
print('{} is not a directory'.format(dir))
out = StringIO()
for cell in CELLS:
xtract_cell_decl(cell, dirs, out)
with open('cells_xtra.v', 'w') as f:
f.write('// Created by cells_xtra.py from Xilinx models\n')
f.write('\n')
f.write(out.getvalue())

155
techlibs/xilinx/cells_xtra.sh
View File

@ -1,155 +0,0 @@
#!/bin/bash
set -e
if [ -z "$1" ]
then
libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
else
libdir=$1
fi
function xtract_cell_decl()
{
for dir in $libdir/xeclib $libdir/retarget; do
[ -f $dir/$1.v ] || continue
[ -z "$2" ] || echo $2
egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
s/^ ((end)?module)/\1/; s/^ / /; /module.*_bb/,/endmodule/ d;'
echo; return
done
echo "Can't find $1."
exit 1
}
{
echo "// Created by cells_xtra.sh from Xilinx models"
echo
# Design elements types listed in Xilinx UG953
xtract_cell_decl BSCANE2 "(* keep *)"
# xtract_cell_decl BUFG "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFGCE "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFGCE_1 "(* clkbuf_driver = \"O\" *)"
#xtract_cell_decl BUFGCTRL "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFGMUX "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFGMUX_1 "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFGMUX_CTRL "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFH "(* clkbuf_driver = \"O\" *)"
#xtract_cell_decl BUFHCE "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFIO "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFMR "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFMRCE "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl BUFR "(* clkbuf_driver = \"O\" *)"
xtract_cell_decl CAPTUREE2 "(* keep *)"
# xtract_cell_decl CARRY4
xtract_cell_decl CFGLUT5 "(* clkbuf_sink = \"CLK\" *)"
xtract_cell_decl DCIRESET "(* keep *)"
xtract_cell_decl DNA_PORT
xtract_cell_decl DSP48E1 "(* clkbuf_sink = \"CLK\" *)"
xtract_cell_decl EFUSE_USR
# xtract_cell_decl FDCE
# xtract_cell_decl FDPE
# xtract_cell_decl FDRE
# xtract_cell_decl FDSE
xtract_cell_decl FIFO18E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
xtract_cell_decl FIFO36E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
xtract_cell_decl FRAME_ECCE2
xtract_cell_decl GTHE2_CHANNEL
xtract_cell_decl GTHE2_COMMON
xtract_cell_decl GTPE2_CHANNEL
xtract_cell_decl GTPE2_COMMON
xtract_cell_decl GTXE2_CHANNEL
xtract_cell_decl GTXE2_COMMON
# xtract_cell_decl IBUF "(* iopad_external_pin = \"I\" *)"
xtract_cell_decl IBUF_IBUFDISABLE "(* iopad_external_pin = \"I\" *)"
xtract_cell_decl IBUF_INTERMDISABLE "(* iopad_external_pin = \"I\" *)"
xtract_cell_decl IBUFDS "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl IBUFDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl IBUFDS_GTE2 "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl IBUFDS_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl IBUFDS_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl IBUFG "(* iopad_external_pin = \"I\" *)"
xtract_cell_decl IBUFGDS "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl IBUFGDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)"
xtract_cell_decl ICAPE2 "(* keep *)"
xtract_cell_decl IDDR "(* clkbuf_sink = \"C\" *)"
xtract_cell_decl IDDR_2CLK "(* clkbuf_sink = \"C,CB\" *)"
xtract_cell_decl IDELAYCTRL "(* keep *) (* clkbuf_sink = \"REFCLK\" *)"
xtract_cell_decl IDELAYE2 "(* clkbuf_sink = \"C\" *)"
xtract_cell_decl IN_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
xtract_cell_decl IOBUF "(* iopad_external_pin = \"IO\" *)"
xtract_cell_decl IOBUF_DCIEN "(* iopad_external_pin = \"IO\" *)"
xtract_cell_decl IOBUF_INTERMDISABLE "(* iopad_external_pin = \"IO\" *)"
xtract_cell_decl IOBUFDS "(* iopad_external_pin = \"IO\" *)"
xtract_cell_decl IOBUFDS_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)"
xtract_cell_decl IOBUFDS_DIFF_OUT "(* iopad_external_pin = \"IO,IOB\" *)"
xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)"
xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"IO,IOB\" *)"
xtract_cell_decl ISERDESE2 "(* clkbuf_sink = \"CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB\" *)"
xtract_cell_decl KEEPER
xtract_cell_decl LDCE
xtract_cell_decl LDPE
# xtract_cell_decl LUT1
# xtract_cell_decl LUT2
# xtract_cell_decl LUT3
# xtract_cell_decl LUT4
# xtract_cell_decl LUT5
# xtract_cell_decl LUT6
#xtract_cell_decl LUT6_2
xtract_cell_decl MMCME2_ADV
xtract_cell_decl MMCME2_BASE
# xtract_cell_decl MUXF7
# xtract_cell_decl MUXF8
# xtract_cell_decl OBUF "(* iopad_external_pin = \"O\" *)"
xtract_cell_decl OBUFDS "(* iopad_external_pin = \"O,OB\" *)"
xtract_cell_decl OBUFT "(* iopad_external_pin = \"O\" *)"
xtract_cell_decl OBUFTDS "(* iopad_external_pin = \"O,OB\" *)"
xtract_cell_decl ODDR "(* clkbuf_sink = \"C\" *)"
xtract_cell_decl ODELAYE2 "(* clkbuf_sink = \"C\" *)"
xtract_cell_decl OSERDESE2 "(* clkbuf_sink = \"CLK,CLKDIV\" *)"
xtract_cell_decl OUT_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
xtract_cell_decl PHASER_IN
xtract_cell_decl PHASER_IN_PHY
xtract_cell_decl PHASER_OUT
xtract_cell_decl PHASER_OUT_PHY
xtract_cell_decl PHASER_REF
xtract_cell_decl PHY_CONTROL
xtract_cell_decl PLLE2_ADV
xtract_cell_decl PLLE2_BASE
xtract_cell_decl PS7 "(* keep *)"
xtract_cell_decl PULLDOWN
xtract_cell_decl PULLUP
#xtract_cell_decl RAM128X1D "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM128X1S "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM256X1S "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM32M "(* clkbuf_sink = \"WCLK\" *)"
#xtract_cell_decl RAM32X1D "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM32X1S "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM32X1S_1 "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM32X2S "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM64M "(* clkbuf_sink = \"WCLK\" *)"
#xtract_cell_decl RAM64X1D "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM64X1S "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM64X1S_1 "(* clkbuf_sink = \"WCLK\" *)"
xtract_cell_decl RAM64X2S "(* clkbuf_sink = \"WCLK\" *)"
# xtract_cell_decl RAMB18E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)"
# xtract_cell_decl RAMB36E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)"
xtract_cell_decl ROM128X1
xtract_cell_decl ROM256X1
xtract_cell_decl ROM32X1
xtract_cell_decl ROM64X1
#xtract_cell_decl SRL16E "(* clkbuf_sink = \"CLK\" *)"
#xtract_cell_decl SRLC32E "(* clkbuf_sink = \"CLK\" *)"
xtract_cell_decl STARTUPE2 "(* keep *)"
xtract_cell_decl USR_ACCESSE2
xtract_cell_decl XADC
} > cells_xtra.new
mv cells_xtra.new cells_xtra.v
exit 0

339
techlibs/xilinx/cells_xtra.v
View File

@ -1,4 +1,4 @@
// Created by cells_xtra.sh from Xilinx models
// Created by cells_xtra.py from Xilinx models
(* keep *)
module BSCANE2 (...);
@ -17,75 +17,79 @@ module BSCANE2 (...);
input TDO;
endmodule
(* clkbuf_driver = "O" *)
module BUFGCE (...);
parameter CE_TYPE = "SYNC";
parameter [0:0] IS_CE_INVERTED = 1'b0;
parameter [0:0] IS_I_INVERTED = 1'b0;
(* clkbuf_driver *)
output O;
input CE;
input I;
endmodule
(* clkbuf_driver = "O" *)
module BUFGCE_1 (...);
(* clkbuf_driver *)
output O;
input CE;
input I;
endmodule
(* clkbuf_driver = "O" *)
module BUFGMUX (...);
parameter CLK_SEL_TYPE = "SYNC";
output O;
input I0, I1, S;
endmodule
(* clkbuf_driver = "O" *)
module BUFGMUX_1 (...);
parameter CLK_SEL_TYPE = "SYNC";
output O;
input I0, I1, S;
endmodule
(* clkbuf_driver = "O" *)
module BUFGMUX_CTRL (...);
(* clkbuf_driver *)
output O;
input I0;
input I1;
input S;
endmodule
module BUFGMUX_1 (...);
parameter CLK_SEL_TYPE = "SYNC";
(* clkbuf_driver *)
output O;
input I0;
input I1;
input S;
endmodule
module BUFGMUX_CTRL (...);
(* clkbuf_driver *)
output O;
input I0;
input I1;
input S;
endmodule
(* clkbuf_driver = "O" *)
module BUFH (...);
(* clkbuf_driver *)
output O;
input I;
endmodule
(* clkbuf_driver = "O" *)
module BUFIO (...);
(* clkbuf_driver *)
output O;
input I;
endmodule
(* clkbuf_driver = "O" *)
module BUFMR (...);
(* clkbuf_driver *)
output O;
input I;
endmodule
(* clkbuf_driver = "O" *)
module BUFMRCE (...);
parameter CE_TYPE = "SYNC";
parameter integer INIT_OUT = 0;
parameter [0:0] IS_CE_INVERTED = 1'b0;
(* clkbuf_driver *)
output O;
input CE;
input I;
endmodule
(* clkbuf_driver = "O" *)
module BUFR (...);
(* clkbuf_driver *)
output O;
input CE;
input CLR;
@ -101,15 +105,21 @@ module CAPTUREE2 (...);
input CLK;
endmodule
(* clkbuf_sink = "CLK" *)
module CFGLUT5 (...);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
output CDO;
output O5;
output O6;
input I4, I3, I2, I1, I0;
input CDI, CE, CLK;
input I4;
input I3;
input I2;
input I1;
input I0;
input CDI;
input CE;
(* clkbuf_sink *)
input CLK;
endmodule
(* keep *)
@ -121,10 +131,12 @@ endmodule
module DNA_PORT (...);
parameter [56:0] SIM_DNA_VALUE = 57'h0;
output DOUT;
input CLK, DIN, READ, SHIFT;
input CLK;
input DIN;
input READ;
input SHIFT;
endmodule
(* clkbuf_sink = "CLK" *)
module DSP48E1 (...);
parameter integer ACASCREG = 1;
parameter integer ADREG = 1;
@ -189,6 +201,7 @@ module DSP48E1 (...);
input CEINMODE;
input CEM;
input CEP;
(* clkbuf_sink *)
input CLK;
input [24:0] D;
input [4:0] INMODE;
@ -212,7 +225,6 @@ module EFUSE_USR (...);
output [31:0] EFUSEUSR;
endmodule
(* clkbuf_sink = "RDCLK,WRCLK" *)
module FIFO18E1 (...);
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
@ -242,16 +254,17 @@ module FIFO18E1 (...);
output WRERR;
input [31:0] DI;
input [3:0] DIP;
(* clkbuf_sink *)
input RDCLK;
input RDEN;
input REGCE;
input RST;
input RSTREG;
(* clkbuf_sink *)
input WRCLK;
input WREN;
endmodule
(* clkbuf_sink = "RDCLK,WRCLK" *)
module FIFO36E1 (...);
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
@ -288,11 +301,13 @@ module FIFO36E1 (...);
input [7:0] DIP;
input INJECTDBITERR;
input INJECTSBITERR;
(* clkbuf_sink *)
input RDCLK;
input RDEN;
input REGCE;
input RST;
input RSTREG;
(* clkbuf_sink *)
input WRCLK;
input WREN;
endmodule
@ -1979,30 +1994,29 @@ module GTXE2_COMMON (...);
input [7:0] PMARSVD;
endmodule
(* iopad_external_pin = "I" *)
module IBUF_IBUFDISABLE (...);
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
output O;
(* iopad_external_pin *)
input I;
input IBUFDISABLE;
endmodule
(* iopad_external_pin = "I" *)
module IBUF_INTERMDISABLE (...);
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
output O;
(* iopad_external_pin *)
input I;
input IBUFDISABLE;
input INTERMDISABLE;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
@ -2012,20 +2026,25 @@ module IBUFDS (...);
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
output O;
input I, IB;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFDS_DIFF_OUT (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
output O, OB;
input I, IB;
output O;
output OB;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2035,12 +2054,13 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
parameter USE_IBUFDISABLE = "TRUE";
output O;
output OB;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
input IBUFDISABLE;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2050,13 +2070,14 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
parameter USE_IBUFDISABLE = "TRUE";
output O;
output OB;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
input IBUFDISABLE;
input INTERMDISABLE;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFDS_GTE2 (...);
parameter CLKCM_CFG = "TRUE";
parameter CLKRCV_TRST = "TRUE";
@ -2064,11 +2085,12 @@ module IBUFDS_GTE2 (...);
output O;
output ODIV2;
input CEB;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFDS_IBUFDISABLE (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2077,12 +2099,13 @@ module IBUFDS_IBUFDISABLE (...);
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
output O;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
input IBUFDISABLE;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFDS_INTERMDISABLE (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2091,23 +2114,24 @@ module IBUFDS_INTERMDISABLE (...);
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
output O;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
input IBUFDISABLE;
input INTERMDISABLE;
endmodule
(* iopad_external_pin = "I" *)
module IBUFG (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
output O;
(* iopad_external_pin *)
input I;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFGDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
@ -2115,17 +2139,23 @@ module IBUFGDS (...);
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
output O;
input I, IB;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
endmodule
(* iopad_external_pin = "I,IB" *)
module IBUFGDS_DIFF_OUT (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
output O, OB;
input I, IB;
output O;
output OB;
(* iopad_external_pin *)
input I;
(* iopad_external_pin *)
input IB;
endmodule
(* keep *)
@ -2140,7 +2170,6 @@ module ICAPE2 (...);
input [31:0] I;
endmodule
(* clkbuf_sink = "C" *)
module IDDR (...);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
@ -2152,6 +2181,7 @@ module IDDR (...);
parameter XON = "TRUE";
output Q1;
output Q2;
(* clkbuf_sink *)
input C;
input CE;
input D;
@ -2159,7 +2189,6 @@ module IDDR (...);
input S;
endmodule
(* clkbuf_sink = "C,CB" *)
module IDDR_2CLK (...);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
@ -2170,7 +2199,9 @@ module IDDR_2CLK (...);
parameter SRTYPE = "SYNC";
output Q1;
output Q2;
(* clkbuf_sink *)
input C;
(* clkbuf_sink *)
input CB;
input CE;
input D;
@ -2178,15 +2209,15 @@ module IDDR_2CLK (...);
input S;
endmodule
(* keep *) (* clkbuf_sink = "REFCLK" *)
(* keep *)
module IDELAYCTRL (...);
parameter SIM_DEVICE = "7SERIES";
output RDY;
(* clkbuf_sink *)
input REFCLK;
input RST;
endmodule
(* clkbuf_sink = "C" *)
module IDELAYE2 (...);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "IDATAIN";
@ -2202,6 +2233,7 @@ module IDELAYE2 (...);
parameter integer SIM_DELAY_D = 0;
output [4:0] CNTVALUEOUT;
output DATAOUT;
(* clkbuf_sink *)
input C;
input CE;
input CINVCTRL;
@ -2214,7 +2246,6 @@ module IDELAYE2 (...);
input REGRST;
endmodule
(* clkbuf_sink = "RDCLK,WRCLK" *)
module IN_FIFO (...);
parameter integer ALMOST_EMPTY_VALUE = 1;
parameter integer ALMOST_FULL_VALUE = 1;
@ -2234,9 +2265,11 @@ module IN_FIFO (...);
output [7:0] Q7;
output [7:0] Q8;
output [7:0] Q9;
(* clkbuf_sink *)
input RDCLK;
input RDEN;
input RESET;
(* clkbuf_sink *)
input WRCLK;
input WREN;
input [3:0] D0;
@ -2251,18 +2284,18 @@ module IN_FIFO (...);
input [7:0] D6;
endmodule
(* iopad_external_pin = "IO" *)
module IOBUF (...);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
(* iopad_external_pin *)
inout IO;
input I, T;
input I;
input T;
endmodule
(* iopad_external_pin = "IO" *)
module IOBUF_DCIEN (...);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
@ -2271,6 +2304,7 @@ module IOBUF_DCIEN (...);
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
output O;
(* iopad_external_pin *)
inout IO;
input DCITERMDISABLE;
input I;
@ -2278,7 +2312,6 @@ module IOBUF_DCIEN (...);
input T;
endmodule
(* iopad_external_pin = "IO" *)
module IOBUF_INTERMDISABLE (...);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
@ -2287,6 +2320,7 @@ module IOBUF_INTERMDISABLE (...);
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
output O;
(* iopad_external_pin *)
inout IO;
input I;
input IBUFDISABLE;
@ -2294,7 +2328,6 @@ module IOBUF_INTERMDISABLE (...);
input T;
endmodule
(* iopad_external_pin = "IO" *)
module IOBUFDS (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2302,11 +2335,13 @@ module IOBUFDS (...);
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
inout IO, IOB;
input I, T;
(* iopad_external_pin *)
inout IO;
inout IOB;
input I;
input T;
endmodule
(* iopad_external_pin = "IO,IOB" *)
module IOBUFDS_DCIEN (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2316,7 +2351,9 @@ module IOBUFDS_DCIEN (...);
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
output O;
(* iopad_external_pin *)
inout IO;
(* iopad_external_pin *)
inout IOB;
input DCITERMDISABLE;
input I;
@ -2324,7 +2361,6 @@ module IOBUFDS_DCIEN (...);
input T;
endmodule
(* iopad_external_pin = "IO,IOB" *)
module IOBUFDS_DIFF_OUT (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2332,14 +2368,15 @@ module IOBUFDS_DIFF_OUT (...);
parameter IOSTANDARD = "DEFAULT";
output O;
output OB;
(* iopad_external_pin *)
inout IO;
(* iopad_external_pin *)
inout IOB;
input I;
input TM;
input TS;
endmodule
(* iopad_external_pin = "IO,IOB" *)
module IOBUFDS_DIFF_OUT_DCIEN (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2349,7 +2386,9 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
parameter USE_IBUFDISABLE = "TRUE";
output O;
output OB;
(* iopad_external_pin *)
inout IO;
(* iopad_external_pin *)
inout IOB;
input DCITERMDISABLE;
input I;
@ -2358,7 +2397,6 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
input TS;
endmodule
(* iopad_external_pin = "IO,IOB" *)
module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
@ -2368,7 +2406,9 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
parameter USE_IBUFDISABLE = "TRUE";
output O;
output OB;
(* iopad_external_pin *)
inout IO;
(* iopad_external_pin *)
inout IOB;
input I;
input IBUFDISABLE;
@ -2377,7 +2417,6 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
input TS;
endmodule
(* clkbuf_sink = "CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB" *)
module ISERDESE2 (...);
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
@ -2417,15 +2456,21 @@ module ISERDESE2 (...);
input BITSLIP;
input CE1;
input CE2;
(* clkbuf_sink *)
input CLK;
(* clkbuf_sink *)
input CLKB;
(* clkbuf_sink *)
input CLKDIV;
(* clkbuf_sink *)
input CLKDIVP;
input D;
input DDLY;
input DYNCLKDIVSEL;
input DYNCLKSEL;
(* clkbuf_sink *)
input OCLK;
(* clkbuf_sink *)
input OCLKB;
input OFB;
input RST;
@ -2444,7 +2489,10 @@ module LDCE (...);
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
input CLR, D, G, GE;
input CLR;
input D;
input G;
input GE;
endmodule
module LDPE (...);
@ -2454,7 +2502,10 @@ module LDPE (...);
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
input D, G, GE, PRE;
input D;
input G;
input GE;
input PRE;
endmodule
module MMCME2_ADV (...);
@ -2598,37 +2649,43 @@ module MMCME2_BASE (...);
input RST;
endmodule
(* iopad_external_pin = "O,OB" *)
module OBUFDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O, OB;
(* iopad_external_pin *)
output O;
(* iopad_external_pin *)
output OB;
input I;
endmodule
(* iopad_external_pin = "O" *)
module OBUFT (...);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
(* iopad_external_pin *)
output O;
input I, T;
input I;
input T;
endmodule
(* iopad_external_pin = "O,OB" *)
module OBUFTDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O, OB;
input I, T;
(* iopad_external_pin *)
output O;
(* iopad_external_pin *)
output OB;
input I;
input T;
endmodule
(* clkbuf_sink = "C" *)
module ODDR (...);
output Q;
(* clkbuf_sink *)
input C;
input CE;
input D1;
@ -2645,7 +2702,6 @@ module ODDR (...);
parameter XON = "TRUE";
endmodule
(* clkbuf_sink = "C" *)
module ODELAYE2 (...);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "ODATAIN";
@ -2660,6 +2716,7 @@ module ODELAYE2 (...);
parameter integer SIM_DELAY_D = 0;
output [4:0] CNTVALUEOUT;
output DATAOUT;
(* clkbuf_sink *)
input C;
input CE;
input CINVCTRL;
@ -2672,7 +2729,6 @@ module ODELAYE2 (...);
input REGRST;
endmodule
(* clkbuf_sink = "CLK,CLKDIV" *)
module OSERDESE2 (...);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
@ -2706,7 +2762,9 @@ module OSERDESE2 (...);
output TBYTEOUT;
output TFB;
output TQ;
(* clkbuf_sink *)
input CLK;
(* clkbuf_sink *)
input CLKDIV;
input D1;
input D2;
@ -2728,7 +2786,6 @@ module OSERDESE2 (...);
input TCE;
endmodule
(* clkbuf_sink = "RDCLK,WRCLK" *)
module OUT_FIFO (...);
parameter integer ALMOST_EMPTY_VALUE = 1;
parameter integer ALMOST_FULL_VALUE = 1;
@ -2749,9 +2806,11 @@ module OUT_FIFO (...);
output [3:0] Q9;
output [7:0] Q5;
output [7:0] Q6;
(* clkbuf_sink *)
input RDCLK;
input RDEN;
input RESET;
(* clkbuf_sink *)
input WRCLK;
input WREN;
input [7:0] D0;
@ -3731,26 +3790,34 @@ module PULLUP (...);
output O;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM128X1S (...);
parameter [127:0] INIT = 128'h00000000000000000000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output O;
input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input D;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM256X1S (...);
parameter [255:0] INIT = 256'h0;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output O;
input [7:0] A;
input D;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM32M (...);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
@ -3769,36 +3836,59 @@ module RAM32M (...);
input [1:0] DIB;
input [1:0] DIC;
input [1:0] DID;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM32X1S (...);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output O;
input A0, A1, A2, A3, A4, D, WCLK, WE;
input A0;
input A1;
input A2;
input A3;
input A4;
input D;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM32X1S_1 (...);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output O;
input A0, A1, A2, A3, A4, D, WCLK, WE;
input A0;
input A1;
input A2;
input A3;
input A4;
input D;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM32X2S (...);
parameter [31:0] INIT_00 = 32'h00000000;
parameter [31:0] INIT_01 = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output O0, O1;
input A0, A1, A2, A3, A4, D0, D1, WCLK, WE;
output O0;
output O1;
input A0;
input A1;
input A2;
input A3;
input A4;
input D0;
input D1;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM64M (...);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
@ -3817,57 +3907,106 @@ module RAM64M (...);
input DIB;
input DIC;
input DID;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM64X1S (...);
parameter [63:0] INIT = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output O;
input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM64X1S_1 (...);
parameter [63:0] INIT = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output O;
input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
(* clkbuf_sink = "WCLK" *)
module RAM64X2S (...);
parameter [63:0] INIT_00 = 64'h0000000000000000;
parameter [63:0] INIT_01 = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output O0, O1;
input A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE;
output O0;
output O1;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D0;
input D1;
(* clkbuf_sink *)
input WCLK;
input WE;
endmodule
module ROM128X1 (...);
parameter [127:0] INIT = 128'h00000000000000000000000000000000;
output O;
input A0, A1, A2, A3, A4, A5, A6;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
endmodule
module ROM256X1 (...);
parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output O;
input A0, A1, A2, A3, A4, A5, A6, A7;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
endmodule
module ROM32X1 (...);
parameter [31:0] INIT = 32'h00000000;
output O;
input A0, A1, A2, A3, A4;
input A0;
input A1;
input A2;
input A3;
input A4;
endmodule
module ROM64X1 (...);
parameter [63:0] INIT = 64'h0000000000000000;
output O;
input A0, A1, A2, A3, A4, A5;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
endmodule
(* keep *)

6
techlibs/xilinx/xc6s_brams_bb.v
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@ -1,6 +1,7 @@
(* clkbuf_sink = "CLKAWRCLK,CLKBRDCLK" *)
module RAMB8BWER (
(* clkbuf_sink *)
input CLKAWRCLK,
(* clkbuf_sink *)
input CLKBRDCLK,
input ENAWREN,
input ENBRDEN,
@ -87,9 +88,10 @@ module RAMB8BWER (
parameter SIM_COLLISION_CHECK = "ALL";
endmodule
(* clkbuf_sink = "CLKA,CLKB" *)
module RAMB16BWER (
(* clkbuf_sink *)
input CLKA,
(* clkbuf_sink *)
input CLKB,
input ENA,
input ENB,

6
techlibs/xilinx/xc7_brams_bb.v
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@ -1,6 +1,7 @@
(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *)
module RAMB18E1 (
(* clkbuf_sink *)
input CLKARDCLK,
(* clkbuf_sink *)
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,
@ -123,9 +124,10 @@ module RAMB18E1 (
parameter SIM_DEVICE = "VIRTEX6";
endmodule
(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *)
module RAMB36E1 (
(* clkbuf_sink *)
input CLKARDCLK,
(* clkbuf_sink *)
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,