mirror of https://github.com/YosysHQ/yosys.git
review fixes
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@ -19,6 +19,9 @@ Yosys 0.9 .. Yosys 0.9-dev
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- Added automatic gzip compression (based on filename extension) for backends
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- Improve attribute and parameter encoding in JSON to avoid ambiguities between
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bit vectors and strings containing [01xz]*
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- Added "clkbufmap" pass
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- Added "synth_xilinx -ise" for Spartan 6 (experimental)
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- "synth_xilinx" now automatically inserts clock buffers
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Yosys 0.8 .. Yosys 0.8-dev
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--------------------------
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@ -2,6 +2,7 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -32,19 +33,6 @@ void split_portname_pair(std::string &port1, std::string &port2)
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}
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}
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std::vector<std::string> split(std::string text, const char *delim)
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{
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std::vector<std::string> list;
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char *p = strdup(text.c_str());
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char *t = strtok(p, delim);
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while (t != NULL) {
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list.push_back(t);
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t = strtok(NULL, delim);
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}
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free(p);
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return list;
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}
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struct ClkbufmapPass : public Pass {
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ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
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void help() YS_OVERRIDE
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@ -127,7 +115,7 @@ struct ClkbufmapPass : public Pass {
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auto it = module->attributes.find("\\clkbuf_driver");
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if (it != module->attributes.end()) {
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auto value = it->second.decode_string();
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for (auto name : split(value, ",")) {
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for (auto name : split_tokens(value, ",")) {
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auto wire = module->wire(RTLIL::escape_id(name));
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if (!wire)
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log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
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@ -138,7 +126,7 @@ struct ClkbufmapPass : public Pass {
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it = module->attributes.find("\\clkbuf_sink");
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if (it != module->attributes.end()) {
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auto value = it->second.decode_string();
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for (auto name : split(value, ",")) {
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for (auto name : split_tokens(value, ",")) {
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auto wire = module->wire(RTLIL::escape_id(name));
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if (!wire)
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log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
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@ -32,19 +32,6 @@ void split_portname_pair(std::string &port1, std::string &port2)
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}
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}
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std::vector<std::string> split(std::string text, const char *delim)
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{
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std::vector<std::string> list;
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char *p = strdup(text.c_str());
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char *t = strtok(p, delim);
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while (t != NULL) {
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list.push_back(t);
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t = strtok(NULL, delim);
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}
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free(p);
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return list;
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}
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struct IopadmapPass : public Pass {
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IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
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void help() YS_OVERRIDE
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@ -190,7 +177,7 @@ struct IopadmapPass : public Pass {
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auto it = module->attributes.find("\\iopad_external_pin");
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if (it != module->attributes.end()) {
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auto value = it->second.decode_string();
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for (auto name : split(value, ",")) {
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for (auto name : split_tokens(value, ",")) {
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ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
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}
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}
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@ -81,12 +81,15 @@ struct SynthXilinxPass : public ScriptPass
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log(" -nowidelut\n");
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log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
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log("\n");
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log(" -iopads\n");
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log(" perform I/O buffer insertion (selected automatically by -ise)\n");
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log(" -iopad\n");
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log(" enable I/O buffer insertion (selected automatically by -ise)\n");
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log("\n");
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log(" -noiopads\n");
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log(" -noiopad\n");
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log(" disable I/O buffer insertion (only useful with -ise)\n");
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log("\n");
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log(" -noclkbuf\n");
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log(" disable automatic clock buffer insertion\n");
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log("\n");
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log(" -widemux <int>\n");
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log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
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log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
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@ -113,7 +116,7 @@ struct SynthXilinxPass : public ScriptPass
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}
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std::string top_opt, edif_file, blif_file, family;
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bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
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bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
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int widemux;
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void clear_flags() YS_OVERRIDE
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@ -126,8 +129,9 @@ struct SynthXilinxPass : public ScriptPass
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retime = false;
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vpr = false;
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ise = false;
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iopads = false;
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noiopads = false;
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iopad = false;
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noiopad = false;
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noclkbuf = false;
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nocarry = false;
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nobram = false;
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nodram = false;
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@ -194,12 +198,16 @@ struct SynthXilinxPass : public ScriptPass
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ise = true;
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continue;
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}
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if (args[argidx] == "-iopads") {
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iopads = true;
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if (args[argidx] == "-iopad") {
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iopad = true;
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continue;
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}
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if (args[argidx] == "-noiopads") {
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noiopads = true;
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if (args[argidx] == "-noiopad") {
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noiopad = true;
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continue;
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}
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if (args[argidx] == "-noclkbuf") {
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noclkbuf = true;
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continue;
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}
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if (args[argidx] == "-nocarry") {
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@ -435,14 +443,15 @@ struct SynthXilinxPass : public ScriptPass
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}
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if (check_label("finalize")) {
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bool do_iopads = iopads || (ise && !noiopads);
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if (help_mode || do_iopads)
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run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')");
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else
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run("clkbufmap -buf BUFG O:I");
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if (do_iopads)
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run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')");
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bool do_iopad = iopad || (ise && !noiopad);
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if (help_mode || !noclkbuf) {
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if (help_mode || do_iopad)
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run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')");
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else
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run("clkbufmap -buf BUFG O:I");
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}
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if (do_iopad)
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run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
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}
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if (check_label("check")) {
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