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review fixes

This commit is contained in:
Marcin Kościelnicki 2019-08-13 00:35:54 +00:00
parent f4c62f33ac
commit c6d5b97b98
4 changed files with 34 additions and 47 deletions
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3
CHANGELOG
View File

@ -19,6 +19,9 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added automatic gzip compression (based on filename extension) for backends
- Improve attribute and parameter encoding in JSON to avoid ambiguities between
bit vectors and strings containing [01xz]*
- Added "clkbufmap" pass
- Added "synth_xilinx -ise" for Spartan 6 (experimental)
- "synth_xilinx" now automatically inserts clock buffers
Yosys 0.8 .. Yosys 0.8-dev
--------------------------

18
passes/techmap/clkbufmap.cc
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@ -2,6 +2,7 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -32,19 +33,6 @@ void split_portname_pair(std::string &port1, std::string &port2)
}
}
std::vector<std::string> split(std::string text, const char *delim)
{
std::vector<std::string> list;
char *p = strdup(text.c_str());
char *t = strtok(p, delim);
while (t != NULL) {
list.push_back(t);
t = strtok(NULL, delim);
}
free(p);
return list;
}
struct ClkbufmapPass : public Pass {
ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
void help() YS_OVERRIDE
@ -127,7 +115,7 @@ struct ClkbufmapPass : public Pass {
auto it = module->attributes.find("\\clkbuf_driver");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split(value, ",")) {
for (auto name : split_tokens(value, ",")) {
auto wire = module->wire(RTLIL::escape_id(name));
if (!wire)
log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
@ -138,7 +126,7 @@ struct ClkbufmapPass : public Pass {
it = module->attributes.find("\\clkbuf_sink");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split(value, ",")) {
for (auto name : split_tokens(value, ",")) {
auto wire = module->wire(RTLIL::escape_id(name));
if (!wire)
log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));

15
passes/techmap/iopadmap.cc
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@ -32,19 +32,6 @@ void split_portname_pair(std::string &port1, std::string &port2)
}
}
std::vector<std::string> split(std::string text, const char *delim)
{
std::vector<std::string> list;
char *p = strdup(text.c_str());
char *t = strtok(p, delim);
while (t != NULL) {
list.push_back(t);
t = strtok(NULL, delim);
}
free(p);
return list;
}
struct IopadmapPass : public Pass {
IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
void help() YS_OVERRIDE
@ -190,7 +177,7 @@ struct IopadmapPass : public Pass {
auto it = module->attributes.find("\\iopad_external_pin");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split(value, ",")) {
for (auto name : split_tokens(value, ",")) {
ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
}
}

45
techlibs/xilinx/synth_xilinx.cc
View File

@ -81,12 +81,15 @@ struct SynthXilinxPass : public ScriptPass
log(" -nowidelut\n");
log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
log("\n");
log(" -iopads\n");
log(" perform I/O buffer insertion (selected automatically by -ise)\n");
log(" -iopad\n");
log(" enable I/O buffer insertion (selected automatically by -ise)\n");
log("\n");
log(" -noiopads\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (only useful with -ise)\n");
log("\n");
log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion\n");
log("\n");
log(" -widemux <int>\n");
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
@ -113,7 +116,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
int widemux;
void clear_flags() YS_OVERRIDE
@ -126,8 +129,9 @@ struct SynthXilinxPass : public ScriptPass
retime = false;
vpr = false;
ise = false;
iopads = false;
noiopads = false;
iopad = false;
noiopad = false;
noclkbuf = false;
nocarry = false;
nobram = false;
nodram = false;
@ -194,12 +198,16 @@ struct SynthXilinxPass : public ScriptPass
ise = true;
continue;
}
if (args[argidx] == "-iopads") {
iopads = true;
if (args[argidx] == "-iopad") {
iopad = true;
continue;
}
if (args[argidx] == "-noiopads") {
noiopads = true;
if (args[argidx] == "-noiopad") {
noiopad = true;
continue;
}
if (args[argidx] == "-noclkbuf") {
noclkbuf = true;
continue;
}
if (args[argidx] == "-nocarry") {
@ -435,14 +443,15 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("finalize")) {
bool do_iopads = iopads || (ise && !noiopads);
if (help_mode || do_iopads)
run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')");
else
run("clkbufmap -buf BUFG O:I");
if (do_iopads)
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')");
bool do_iopad = iopad || (ise && !noiopad);
if (help_mode || !noclkbuf) {
if (help_mode || do_iopad)
run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')");
else
run("clkbufmap -buf BUFG O:I");
}
if (do_iopad)
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
}
if (check_label("check")) {