mirror of https://github.com/YosysHQ/yosys.git
Add (* abc_arrival *) attribute
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@ -86,6 +86,7 @@ struct XAigerWriter
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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vector<SigBit> ff_bits;
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dict<SigBit, float> arrival_times;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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@ -217,7 +218,12 @@ struct XAigerWriter
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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dict<IdString, std::pair<IdString,IdString>> flop_data;
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struct flop_data_t {
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IdString d_port;
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IdString q_port;
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int q_arrival;
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};
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dict<IdString, flop_data_t> flop_data;
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bool abc_box_seen = false;
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for (auto cell : module->selected_cells()) {
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@ -272,9 +278,10 @@ struct XAigerWriter
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toposort.node(cell->name);
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auto r = flop_data.insert(std::make_pair(cell->type, std::make_pair(IdString(), IdString())));
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auto r = flop_data.insert(std::make_pair(cell->type, flop_data_t{IdString(), IdString(), 0}));
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if (r.second && inst_module->attributes.count("\\abc_flop")) {
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IdString abc_flop_d, abc_flop_q;
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IdString &abc_flop_d = r.first->second.d_port;
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IdString &abc_flop_q = r.first->second.q_port;
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for (auto port_name : inst_module->ports) {
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auto wire = inst_module->wire(port_name);
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log_assert(wire);
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@ -287,16 +294,22 @@ struct XAigerWriter
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if (abc_flop_q != IdString())
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log_error("More than one port has the 'abc_flop_q' attribute set on module '%s'.\n", log_id(cell->type));
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abc_flop_q = port_name;
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auto it = wire->attributes.find("\\abc_arrival");
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if (it != wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
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r.first->second.q_arrival = it->second.as_int();
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}
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}
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}
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if (abc_flop_d == IdString())
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log_error("'abc_flop_d' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
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if (abc_flop_q == IdString())
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log_error("'abc_flop_q' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
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r.first->second = std::make_pair(abc_flop_d, abc_flop_q);
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}
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auto abc_flop_d = r.first->second.first;
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auto abc_flop_d = r.first->second.d_port;
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if (abc_flop_d != IdString()) {
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SigBit d = cell->getPort(abc_flop_d);
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SigBit I = sigmap(d);
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@ -304,13 +317,17 @@ struct XAigerWriter
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alias_map[I] = d;
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unused_bits.erase(d);
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auto abc_flop_q = r.first->second.second;
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auto abc_flop_q = r.first->second.q_port;
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SigBit q = cell->getPort(abc_flop_q);
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SigBit O = sigmap(q);
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if (O != q)
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alias_map[O] = q;
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undriven_bits.erase(O);
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ff_bits.emplace_back(q);
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auto arrival = r.first->second.q_arrival;
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if (arrival)
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arrival_times[q] = arrival;
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}
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for (const auto &conn : cell->connections()) {
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@ -330,12 +347,22 @@ struct XAigerWriter
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bool cell_known = cell->known();
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for (const auto &c : cell->connections()) {
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if (c.second.is_fully_const()) continue;
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auto is_input = !cell_known || cell->input(c.first);
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auto is_output = !cell_known || cell->output(c.first);
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auto port_wire = inst_module->wire(c.first);
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log_assert(port_wire);
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auto is_input = !cell_known || port_wire->port_input;
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auto is_output = !cell_known || port_wire->port_output;
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if (!is_input && !is_output)
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log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
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if (is_input) {
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int arrival = 0;
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auto it = port_wire->attributes.find("\\abc_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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}
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for (auto b : c.second.bits()) {
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Wire *w = b.wire;
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if (!w) continue;
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@ -349,6 +376,8 @@ struct XAigerWriter
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if (!cell_known)
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keep_bits.insert(b);
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}
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if (arrival)
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arrival_times[b] = arrival;
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}
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}
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if (is_output) {
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@ -362,6 +391,8 @@ struct XAigerWriter
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undriven_bits.erase(O);
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}
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}
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}
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}
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@ -722,6 +753,9 @@ struct XAigerWriter
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int32_t i32_be = to_big_endian(i32);
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buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
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};
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auto write_buffer_float = [](std::stringstream &buffer, float f32) {
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buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
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};
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std::stringstream h_buffer;
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auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
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@ -806,13 +840,25 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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std::stringstream i_buffer;
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auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
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for (auto i : input_bits)
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write_i_buffer(arrival_times.at(i, 0));
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//std::stringstream o_buffer;
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//auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
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//for (auto o : output_bits)
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// write_o_buffer(0);
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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log_debug("flopNum = %d\n", GetSize(ff_bits));
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write_r_buffer(ff_bits.size());
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int mergeability_class = 1;
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for (auto cell : ff_bits)
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for (auto i : ff_bits) {
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write_r_buffer(mergeability_class++);
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write_i_buffer(arrival_times.at(i, 0));
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//write_o_buffer(0);
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}
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f << "r";
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buffer_str = r_buffer.str();
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@ -820,6 +866,17 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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f << "i";
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buffer_str = i_buffer.str();
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buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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//f << "o";
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//buffer_str = o_buffer.str();
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//buffer_size_be = to_big_endian(buffer_str.size());
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//f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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//f.write(buffer_str.data(), buffer_str.size());
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std::stringstream s_buffer;
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auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
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write_s_buffer(ff_bits.size());
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@ -965,7 +965,7 @@ struct Abc9Pass : public Pass {
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vector<int> lut_costs;
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markgroups = false;
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#if 0
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#if 1
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cleanup = false;
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show_tempdir = true;
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#endif
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