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AND with an inverted input, causes X{,N}OR output to be inverted too

This commit is contained in:
Eddie Hung 2019-08-14 16:26:24 -07:00
parent 1e47e81869
commit 1551e14d2d
1 changed files with 2 additions and 2 deletions
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4
passes/techmap/extract_fa.cc
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@ -513,13 +513,13 @@ struct ExtractFaWorker
}
if (func2.at(key).count(xor2_func)) {
SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y;
for (auto bit : func2.at(key).at(xor2_func))
assign_new_driver(bit, YY);
}
if (func2.at(key).count(xnor2_func)) {
SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y);
for (auto bit : func2.at(key).at(xnor2_func))
assign_new_driver(bit, YY);
}