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Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro

This commit is contained in:
Eddie Hung 2019-08-19 09:56:17 -07:00
parent 5abe133323
commit d81a090d89
4 changed files with 12 additions and 12 deletions
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12
passes/techmap/abc9.cc
View File

@ -1088,25 +1088,25 @@ struct Abc9Pass : public Pass {
if (w->port_input) {
if (w->attributes.count(ID(abc_scc_break)))
scc_break_inputs[m->name].insert(p);
if (w->attributes.count(ID(abc_carry_in))) {
if (w->attributes.count(ID(abc_carry))) {
if (carry_in)
log_error("Module '%s' contains more than one 'abc_carry_in' port.\n", log_id(m));
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
carry_in = w;
}
}
if (w->port_output) {
if (w->attributes.count(ID(abc_carry_out))) {
if (w->attributes.count(ID(abc_carry))) {
if (carry_out)
log_error("Module '%s' contains more than one 'abc_carry_out' port.\n", log_id(m));
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
carry_out = w;
}
}
}
if (carry_in || carry_out) {
if (carry_in && !carry_out)
log_error("Module '%s' contains an 'abc_carry_in' port but no 'abc_carry_out' port.\n", log_id(m));
log_error("Module '%s' contains an 'abc_carry' input port but no output port.\n", log_id(m));
if (!carry_in && carry_out)
log_error("Module '%s' contains an 'abc_carry_out' port but no 'abc_carry_in' port.\n", log_id(m));
log_error("Module '%s' contains an 'abc_carry' output port but no input port.\n", log_id(m));
// Make carry_in the last PI, and carry_out the last PO
// since ABC requires it this way
auto &ports = m->ports;

4
techlibs/ecp5/cells_sim.v
View File

@ -17,10 +17,10 @@ endmodule
// ---------------------------------------
(* abc_box_id=1, lib_whitebox *)
module CCU2C(
(* abc_carry_in *) input CIN,
(* abc_carry *) input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
(* abc_carry_out *) output COUT
(* abc_carry *) output COUT
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;

4
techlibs/ice40/cells_sim.v
View File

@ -143,11 +143,11 @@ endmodule
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry_out *) output CO,
(* abc_carry *) output CO,
output O,
input A,
input B,
(* abc_carry_in *) input CI
(* abc_carry *) input CI
);
SB_CARRY carry (
.I0(A),

4
techlibs/xilinx/cells_sim.v
View File

@ -183,9 +183,9 @@ endmodule
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
(* abc_carry_out *) output [3:0] CO,
(* abc_carry *) output [3:0] CO,
output [3:0] O,
(* abc_carry_in *) input CI,
(* abc_carry *) input CI,
input CYINIT,
input [3:0] DI, S
);