Clifford Wolf
|
2aeb4d4e12
|
Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-26 15:20:27 +01:00 |
Clifford Wolf
|
9cd9f5fc78
|
Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-26 15:02:03 +01:00 |
Clifford Wolf
|
d1cb5150aa
|
Add "SVA syntax cheat sheet" comment to verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-26 14:31:58 +01:00 |
Clifford Wolf
|
eb67a7532b
|
Add $allconst and $allseq cell types
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-23 13:14:47 +01:00 |
Clifford Wolf
|
2521ed305e
|
Add Verific SVA support for ranges in repetition operator
|
2018-02-22 12:37:30 +01:00 |
Clifford Wolf
|
6d12c83d36
|
Add support for SVA throughout via Verific
|
2018-02-21 13:09:47 +01:00 |
Clifford Wolf
|
5c6247dfa6
|
Add support for SVA sequence concatenation ranges via verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-18 16:35:06 +01:00 |
Clifford Wolf
|
9d963cd29c
|
Add support for SVA until statements via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-18 14:57:52 +01:00 |
Clifford Wolf
|
5fa2aa2741
|
Move Verific SVA importer to extra C++ source file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-18 13:52:49 +01:00 |
Clifford Wolf
|
c4bf34f6ce
|
Merge Verific SVA preprocessor and SVA importer
|
2018-02-18 13:28:08 +01:00 |
Clifford Wolf
|
68a829dbcd
|
Merge branch 'master' of github.com:cliffordwolf/yosys
|
2018-02-16 14:22:11 +01:00 |
Clifford Wolf
|
2c95dfcb5b
|
Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-15 17:36:08 +01:00 |
Clifford Wolf
|
bc8ab3ab44
|
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
|
2018-02-15 15:26:37 +01:00 |
Clifford Wolf
|
6c00e064e2
|
Fix single-bit $stable handling in verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-01 12:51:49 +01:00 |
Clifford Wolf
|
9af40faa0b
|
Add Verific attribute handling for assert/assume/cover/live/fair cells
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-01-31 19:06:51 +01:00 |
Clifford Wolf
|
675f53abbb
|
Fix permissions on verific vdb files
|
2018-01-28 18:52:01 +01:00 |
Clifford Wolf
|
1d8161b432
|
Fixed handling of synchronous and asynchronous assertion/assumption/cover in verific bindings
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-01-23 17:42:40 +01:00 |
Clifford Wolf
|
a96c775a73
|
Add support for "yosys -E"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-01-07 16:36:13 +01:00 |
Clifford Wolf
|
26c4323d48
|
Merge pull request #479 from Fatsie/latch_without_data
Some standard cell libraries include a latch with only set/reset.
|
2018-01-05 23:00:28 +01:00 |
Clifford Wolf
|
c80315cea4
|
Bugfix in hierarchy handling of blackbox module ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-01-05 13:28:45 +01:00 |
Staf Verhaegen
|
5126c6f22b
|
Some standard cell libraries include a latch with only set/reset.
|
2018-01-03 21:36:02 +00:00 |
Clifford Wolf
|
34005348b6
|
Bugfix in verilog_defaults argument parser
|
2017-12-24 17:21:37 +01:00 |
Clifford Wolf
|
ba90e08398
|
Add support for Verific PRIM_SVA_NOT properties
|
2017-12-10 01:10:03 +01:00 |
Clifford Wolf
|
e4a4c0e10c
|
Add Verific OPER_SVA_STABLE support
|
2017-12-10 00:59:44 +01:00 |
Clifford Wolf
|
27916105a9
|
Refactoring Verific SVA rewriter
|
2017-12-10 00:26:26 +01:00 |
Clifford Wolf
|
8364f509e3
|
Fix error handling for nested always/initial
|
2017-12-02 18:52:05 +01:00 |
Clifford Wolf
|
777f2881d8
|
Add Verilog "automatic" keyword (ignored in synthesis)
|
2017-11-23 08:51:38 +01:00 |
Clifford Wolf
|
5b6e52118c
|
Accept real-valued delay values
|
2017-11-18 10:01:30 +01:00 |
William D. Jones
|
abc5b4b8ce
|
Accommodate Windows-style paths during include-file processing.
|
2017-11-14 16:16:24 -05:00 |
Clifford Wolf
|
a8cf431d9c
|
Remove vhdl2verilog
|
2017-10-25 14:50:22 +02:00 |
Clifford Wolf
|
0a31a0b3ae
|
Remove all PSL support code from verific.cc
|
2017-10-20 13:14:04 +02:00 |
Clifford Wolf
|
1954c78ea7
|
Add "verific -vlog-libdir"
|
2017-10-13 20:23:19 +02:00 |
Clifford Wolf
|
e7a3c47cc7
|
Add "verific -vlog-incdir" and "verific -vlog-define"
|
2017-10-13 20:12:51 +02:00 |
Clifford Wolf
|
05068af880
|
Update Verific README
|
2017-10-13 17:11:53 +02:00 |
Clifford Wolf
|
bc5cc4e103
|
Add Verific fairness/liveness support
|
2017-10-12 12:00:09 +02:00 |
Clifford Wolf
|
12c10892e6
|
Merge branch 'master' of github.com:cliffordwolf/yosys
|
2017-10-10 15:16:45 +02:00 |
Clifford Wolf
|
c10e96c9ec
|
Start work on pre-processor for Verific SVA properties
|
2017-10-10 15:16:39 +02:00 |
Clifford Wolf
|
bc80426d45
|
Remove some dead code
|
2017-10-10 12:00:48 +02:00 |
Clifford Wolf
|
caa78388cd
|
Allow $past, $stable, $rose, $fell in $global_clock blocks
|
2017-10-10 11:59:32 +02:00 |
Clifford Wolf
|
fc3378916d
|
Improve handling of Verific errors
|
2017-10-05 14:38:32 +02:00 |
Clifford Wolf
|
ee56a887b6
|
Improve Verific error handling, check VHDL static asserts
|
2017-10-04 18:56:28 +02:00 |
Clifford Wolf
|
b92ff2706e
|
Fix nasty bug in Verific bindings
|
2017-10-04 17:23:42 +02:00 |
Clifford Wolf
|
a381188b92
|
Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys
|
2017-10-03 18:23:45 +02:00 |
Udi Finkelstein
|
eb40278a16
|
Turned a few member functions into const, esp. dumpAst(), dumpVlog().
|
2017-09-30 07:37:38 +03:00 |
Udi Finkelstein
|
72a08eca3d
|
Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution
(Oreilly 'Flex & Bison' page 189)
|
2017-09-30 06:39:07 +03:00 |
Clifford Wolf
|
dbfd8460a9
|
Allow $size and $bits in verilog mode, actually check test case
|
2017-09-29 11:56:43 +02:00 |
Udi Finkelstein
|
e951ac0dfb
|
$size() now works correctly for all cases!
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
|
2017-09-26 20:34:24 +03:00 |
Udi Finkelstein
|
6ddc6a7af4
|
$size() seems to work now with or without the optional parameter.
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
|
2017-09-26 19:18:25 +03:00 |
Udi Finkelstein
|
7e391ba904
|
enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog
|
2017-09-26 09:19:56 +03:00 |
Udi Finkelstein
|
2dea42e903
|
Added $bits() for memories as well.
|
2017-09-26 09:11:25 +03:00 |
Udi Finkelstein
|
17f8b41605
|
$size() now works with memories as well!
|
2017-09-26 08:36:45 +03:00 |
Udi Finkelstein
|
64eb8f29ad
|
Add $size() function. At the moment it works only on expressions, not on memories.
|
2017-09-26 06:25:42 +03:00 |
Clifford Wolf
|
30396270a2
|
Increase maximum LUT size in blifparse to 12 bits
|
2017-09-27 15:27:42 +02:00 |
Clifford Wolf
|
91d9c50bb3
|
Parse reals as string in JSON front-end
|
2017-09-26 14:37:03 +02:00 |
Clifford Wolf
|
2c04d883b1
|
Minor coding style fix
|
2017-09-26 13:50:14 +02:00 |
Clifford Wolf
|
cb1d439d10
|
Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master
|
2017-09-26 13:48:13 +02:00 |
Clifford Wolf
|
2cc09161ff
|
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
|
2017-09-26 01:52:59 +02:00 |
combinatorylogic
|
64ca0be971
|
Adding support for string macros and macros with arguments after include
|
2017-09-21 18:25:02 +01:00 |
Robert Ou
|
366ce87cff
|
json: Parse inout correctly rather than as an output
|
2017-08-14 12:09:03 -07:00 |
Clifford Wolf
|
15073790bf
|
Add merging of "past FFs" to verific importer
|
2017-07-29 00:10:38 +02:00 |
Clifford Wolf
|
d4b9602cbd
|
Add minimal support for PSL in VHDL via Verific
|
2017-07-28 17:39:49 +02:00 |
Clifford Wolf
|
5a828fff34
|
Improve Verific HDL language options
|
2017-07-28 15:32:54 +02:00 |
Clifford Wolf
|
acd6cfaf67
|
Fix handling of non-user-declared Verific netbus
|
2017-07-28 11:31:27 +02:00 |
Clifford Wolf
|
c1cfca8f54
|
Improve Verific SVA importer
|
2017-07-27 14:05:09 +02:00 |
Clifford Wolf
|
2336d5508b
|
Add log_warning_noprefix() API, Use for Verific warnings and errors
|
2017-07-27 12:17:04 +02:00 |
Clifford Wolf
|
d9641621d9
|
Add "verific -import -n" and "verific -import -nosva"
|
2017-07-27 11:54:45 +02:00 |
Clifford Wolf
|
90d8329f64
|
Improve Verific SVA import: negedge and $past
|
2017-07-27 11:40:07 +02:00 |
Clifford Wolf
|
147ff96ba3
|
Improve Verific SVA importer
|
2017-07-27 10:39:39 +02:00 |
Clifford Wolf
|
530040ba6f
|
Improve Verific bindings (mostly related to SVA)
|
2017-07-26 18:00:01 +02:00 |
Clifford Wolf
|
abd3b4e8e7
|
Improve "help verific" message
|
2017-07-25 15:13:22 +02:00 |
Clifford Wolf
|
6dbe1d4c92
|
Add "verific -extnets"
|
2017-07-25 14:53:11 +02:00 |
Clifford Wolf
|
c97c92e4ec
|
Improve "verific -all" handling
|
2017-07-25 13:33:25 +02:00 |
Clifford Wolf
|
41be530c4e
|
Add "verific -import -d <dump_file"
|
2017-07-24 13:57:16 +02:00 |
Clifford Wolf
|
92d3aad670
|
Add "verific -import -flatten" and "verific -import -v"
|
2017-07-24 11:29:06 +02:00 |
Clifford Wolf
|
5be535517c
|
Add "verific -import -k"
|
2017-07-22 16:16:44 +02:00 |
Clifford Wolf
|
2785aaffeb
|
Improve docs for verific bindings, add simply sby example
|
2017-07-22 11:58:51 +02:00 |
Clifford Wolf
|
36cf18ac4c
|
Fix "read_blif -wideports" handling of cells with wide ports
|
2017-07-21 16:21:12 +02:00 |
Clifford Wolf
|
26766da343
|
Add a paragraph about pre-defined macros to read_verilog help message
|
2017-07-21 14:34:53 +02:00 |
Clifford Wolf
|
9557fd2a36
|
Add attributes and parameter support to JSON front-end
|
2017-07-10 13:17:38 +02:00 |
Clifford Wolf
|
4b2d1fe688
|
Add JSON front-end
|
2017-07-08 16:40:40 +02:00 |
Clifford Wolf
|
28039c3063
|
Add Verific Release information to log
|
2017-07-04 20:01:30 +02:00 |
Clifford Wolf
|
8f8baccfde
|
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
|
2017-06-07 12:30:24 +02:00 |
Clifford Wolf
|
129984e115
|
Fix handling of Verilog ~& and ~| operators
|
2017-06-01 12:43:21 +02:00 |
Clifford Wolf
|
e91548b33e
|
Add support for localparam in module header
|
2017-04-30 17:20:30 +02:00 |
Clifford Wolf
|
f0db8ffdbc
|
Add support for `resetall compiler directive
|
2017-04-26 16:09:41 +02:00 |
Clifford Wolf
|
088f9c9cab
|
Fix verilog pre-processor for multi-level relative includes
|
2017-03-14 17:30:20 +01:00 |
Clifford Wolf
|
5b3b5ffc8c
|
Allow $anyconst, etc. in non-formal SV mode
|
2017-03-01 10:47:05 +01:00 |
Clifford Wolf
|
5f1d0b1024
|
Add $live and $fair cell types, add support for s_eventually keyword
|
2017-02-25 10:36:39 +01:00 |
Clifford Wolf
|
00dba4c197
|
Add support for SystemVerilog unique, unique0, and priority case
|
2017-02-23 16:33:19 +01:00 |
Clifford Wolf
|
1e927a51d5
|
Preserve string parameters
|
2017-02-23 15:39:13 +01:00 |
Clifford Wolf
|
34d4e72132
|
Added SystemVerilog support for ++ and --
|
2017-02-23 11:21:33 +01:00 |
Clifford Wolf
|
4fb8007171
|
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
|
2017-02-14 15:10:59 +01:00 |
Clifford Wolf
|
cdb6ceb8c6
|
Add support for verific mem initialization
|
2017-02-11 15:57:36 +01:00 |
Clifford Wolf
|
c449f4b86f
|
Fix another stupid bug in the same line
|
2017-02-11 11:47:51 +01:00 |
Clifford Wolf
|
fa4a7efe15
|
Add verific support for initialized variables
|
2017-02-11 11:40:18 +01:00 |
Clifford Wolf
|
0b7aac645c
|
Improve handling of Verific warnings and error messages
|
2017-02-11 11:39:50 +01:00 |
Clifford Wolf
|
eb7b18e897
|
Fix extremely stupid typo
|
2017-02-11 11:09:07 +01:00 |
Clifford Wolf
|
848062088c
|
Add checker support to verilog front-end
|
2017-02-09 13:51:44 +01:00 |
Clifford Wolf
|
2ca8d483dd
|
Add "rand" and "rand const" verific support
|
2017-02-09 12:53:46 +01:00 |
Clifford Wolf
|
ef4a28e112
|
Add SV "rand" and "const rand" support
|
2017-02-08 14:38:15 +01:00 |
Clifford Wolf
|
1d1f56a361
|
Add PSL parser mode to verific front-end
|
2017-02-08 10:40:33 +01:00 |
Clifford Wolf
|
7e0b776a79
|
Add "read_blif -wideports"
|
2017-02-06 14:48:03 +01:00 |
Clifford Wolf
|
6abf79eb28
|
Further improve cover() support
|
2017-02-04 17:02:13 +01:00 |
Clifford Wolf
|
3928482a3c
|
Add $cover cell type and SVA cover() support
|
2017-02-04 14:14:26 +01:00 |
Clifford Wolf
|
911c44d164
|
Add assert/assume support to verific front-end
|
2017-02-04 13:36:00 +01:00 |
Clifford Wolf
|
fea528280b
|
Add "enum" and "typedef" lexer support
|
2017-01-17 17:33:52 +01:00 |
Clifford Wolf
|
78f65f89ff
|
Fix bug in AstNode::mem2reg_as_needed_pass2()
|
2017-01-15 13:52:50 +01:00 |
Clifford Wolf
|
2d32c6c4f6
|
Fixed handling of local memories in functions
|
2017-01-05 13:19:03 +01:00 |
Clifford Wolf
|
81a9ee2360
|
Added handling of local memories and error for local decls in unnamed blocks
|
2017-01-04 16:03:04 +01:00 |
Clifford Wolf
|
dfb461fe52
|
Added Verilog $rtoi and $itor support
|
2017-01-03 17:40:58 +01:00 |
Clifford Wolf
|
3886669ab6
|
Added "verilog_defines" command
|
2016-12-15 17:49:28 +01:00 |
Clifford Wolf
|
ecdc22b06c
|
Added support for macros as include file names
|
2016-11-28 14:50:17 +01:00 |
Clifford Wolf
|
c7f6fb6e17
|
Bugfix in "read_verilog -D NAME=VAL" handling
|
2016-11-28 14:45:05 +01:00 |
Clifford Wolf
|
70d7a02cae
|
Added support for hierarchical defparams
|
2016-11-15 13:35:19 +01:00 |
Clifford Wolf
|
a926a6afc2
|
Remember global declarations and defines accross read_verilog calls
|
2016-11-15 12:42:43 +01:00 |
Clifford Wolf
|
2874914bcb
|
Fixed anonymous genblock object names
|
2016-11-04 07:46:30 +01:00 |
Clifford Wolf
|
56e2bb88ae
|
Some fixes in handling of signed arrays
|
2016-11-01 23:17:43 +01:00 |
Clifford Wolf
|
aa72262330
|
Added avail params to ilang format, check module params in 'hierarchy -check'
|
2016-10-22 11:05:49 +02:00 |
Clifford Wolf
|
042b67f024
|
No limit for length of lines in BLIF front-end
|
2016-10-19 12:44:58 +02:00 |
Clifford Wolf
|
bdc316db50
|
Added $anyseq cell type
|
2016-10-14 15:24:03 +02:00 |
Clifford Wolf
|
53655d173b
|
Added $global_clock verilog syntax support for creating $ff cells
|
2016-10-14 12:33:56 +02:00 |
Clifford Wolf
|
8ebba8a35f
|
Added $ff and $_FF_ cell types
|
2016-10-12 01:18:39 +02:00 |
Clifford Wolf
|
8f5bf6de32
|
Added liberty parser support for types within cell decls
|
2016-09-23 13:53:23 +02:00 |
Clifford Wolf
|
aaa99c35bd
|
Added $past, $stable, $rose, $fell SVA functions
|
2016-09-19 01:30:07 +02:00 |
Clifford Wolf
|
13a03b84d4
|
Added support for bus interfaces to "read_liberty -lib"
|
2016-09-18 18:48:59 +02:00 |
Clifford Wolf
|
ab18e9df7c
|
Added assertpmux
|
2016-09-07 00:28:01 +02:00 |
Clifford Wolf
|
d55a93b39f
|
Bugfix in parsing of BLIF latch init values
|
2016-09-06 17:35:06 +02:00 |
Clifford Wolf
|
97583ab729
|
Avoid creation of bogus initial blocks for assert/assume in always @*
|
2016-09-06 17:34:42 +02:00 |
Clifford Wolf
|
aa25a4cec6
|
Added $anyconst support to yosys-smtbmc
|
2016-08-30 19:27:42 +02:00 |
Clifford Wolf
|
6f41e5277d
|
Removed $aconst cell type
|
2016-08-30 19:09:56 +02:00 |
Clifford Wolf
|
eae390ae17
|
Removed $predict again
|
2016-08-28 21:35:33 +02:00 |
Clifford Wolf
|
1276c87a56
|
Added read_verilog -norestrict -assume-asserts
|
2016-08-26 23:35:27 +02:00 |
Clifford Wolf
|
4be4969bae
|
Improved verilog parser errors
|
2016-08-25 11:44:37 +02:00 |
Clifford Wolf
|
cd18235f30
|
Added SV "restrict" keyword
|
2016-08-24 15:30:08 +02:00 |
Clifford Wolf
|
450f6f59b4
|
Fixed bug with memories that do not have a down-to-zero data width
|
2016-08-22 14:27:46 +02:00 |
Clifford Wolf
|
82a4a0230f
|
Another bugfix in mem2reg code
|
2016-08-21 13:23:58 +02:00 |
Clifford Wolf
|
dbdd8927e7
|
Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()
|
2016-08-21 13:18:09 +02:00 |
Clifford Wolf
|
fe9315b7a1
|
Fixed finish_addr handling in $readmemh/$readmemb
|
2016-08-20 13:47:46 +02:00 |
Clifford Wolf
|
f6629b9c29
|
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
|
2016-08-19 18:38:25 +02:00 |
Clifford Wolf
|
e9fe57c75e
|
Only allow posedge/negedge with 1 bit wide signals
|
2016-08-10 19:32:11 +02:00 |
Clifford Wolf
|
7f755dec75
|
Fixed bug in parsing real constants
|
2016-08-06 13:16:23 +02:00 |
Clifford Wolf
|
4056312987
|
Added $anyconst and $aconst
|
2016-07-27 15:41:22 +02:00 |
Clifford Wolf
|
a7b0769623
|
Added "read_verilog -dump_rtlil"
|
2016-07-27 15:40:17 +02:00 |
Clifford Wolf
|
5b944ef11b
|
Fixed a verilog parser memory leak
|
2016-07-25 16:37:58 +02:00 |
Clifford Wolf
|
7a67add95d
|
Fixed parsing of empty positional cell ports
|
2016-07-25 12:48:03 +02:00 |
Clifford Wolf
|
9aae1d1e8f
|
No tristate warning message for "read_verilog -lib"
|
2016-07-23 11:56:53 +02:00 |
Clifford Wolf
|
7fef5ff104
|
Using $initstate in "initial assume" and "initial assert"
|
2016-07-21 14:37:28 +02:00 |
Clifford Wolf
|
5c166e76e5
|
Added $initstate cell type and vlog function
|
2016-07-21 14:23:22 +02:00 |
Clifford Wolf
|
d7763634b6
|
After reading the SV spec, using non-standard predict() instead of expect()
|
2016-07-21 13:34:33 +02:00 |
Clifford Wolf
|
721f1f5ecf
|
Added basic support for $expect cells
|
2016-07-13 16:56:17 +02:00 |
Clifford Wolf
|
9a101dc1f7
|
Fixed mem assignment in left-hand-side concatenation
|
2016-07-08 14:31:06 +02:00 |
Ruben Undheim
|
545bcb37e8
|
Allow defining input ports as "input logic" in SystemVerilog
|
2016-06-20 20:16:37 +02:00 |
Clifford Wolf
|
9bca8ccd40
|
Merge branch 'sv_packages' of https://github.com/rubund/yosys
|
2016-06-19 15:48:40 +02:00 |
Ruben Undheim
|
a8200a773f
|
A few modifications after pull request comments
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
|
2016-06-18 14:23:38 +02:00 |
Clifford Wolf
|
9e28290b0f
|
Added "read_blif -sop"
|
2016-06-18 12:33:13 +02:00 |
Ruben Undheim
|
178ff3e7f6
|
Added support for SystemVerilog packages with localparam definitions
|
2016-06-18 10:53:55 +02:00 |
Clifford Wolf
|
52bb1b968d
|
Added $sop cell type and "abc -sop"
|
2016-06-17 13:50:09 +02:00 |
Clifford Wolf
|
766032c5f8
|
Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
|
2016-05-27 17:55:03 +02:00 |
Clifford Wolf
|
ee071586c5
|
Fixed access-after-delete bug in mem2reg code
|
2016-05-27 17:25:33 +02:00 |
Clifford Wolf
|
e9ceec26ff
|
fixed typos in error messages
|
2016-05-27 16:37:36 +02:00 |
Clifford Wolf
|
060bf4819a
|
Small improvements in Verilog front-end docs
|
2016-05-20 16:21:35 +02:00 |
Clifford Wolf
|
570014800a
|
Include <cmath> in yosys.h
|
2016-05-08 10:50:39 +02:00 |
Clifford Wolf
|
779e2cc819
|
Added support for "active high" and "active low" latches in BLIF front-end
|
2016-04-22 18:02:55 +02:00 |
Clifford Wolf
|
0bc95f1e04
|
Added "yosys -D" feature
|
2016-04-21 23:28:37 +02:00 |
Clifford Wolf
|
5a09fa4553
|
Fixed handling of parameters and const functions in casex/casez pattern
|
2016-04-21 15:31:54 +02:00 |
Clifford Wolf
|
5328a85149
|
Do not set "nosync" on task outputs, fixes #134
|
2016-03-24 12:16:47 +01:00 |
Clifford Wolf
|
4f0d4899ce
|
Added support for $stop system task
|
2016-03-21 16:19:51 +01:00 |
Clifford Wolf
|
e5d42ebb4d
|
Added $display %m support, fixed mem leak in $display, fixes #128
|
2016-03-19 11:51:13 +01:00 |
Clifford Wolf
|
ef4207d5ad
|
Fixed localparam signdness, fixes #127
|
2016-03-18 12:15:00 +01:00 |
Clifford Wolf
|
b6d08f39ba
|
Set "nosync" attribute on internal task/function wires
|
2016-03-18 10:53:29 +01:00 |
Clifford Wolf
|
33c10350b2
|
Fixed Verilog parser fix and more similar improvements
|
2016-03-15 12:22:31 +01:00 |
Andrew Becker
|
81d4e9e7c1
|
Use left-recursive rule for cell_port_list in Verilog parser.
|
2016-03-15 12:03:40 +01:00 |
Clifford Wolf
|
35a6ad4cc1
|
Fixed typos in verilog_defaults help message
|
2016-03-10 11:14:51 +01:00 |
Clifford Wolf
|
22c549ab37
|
Fixed BLIF parser for empty port assignments
|
2016-02-24 09:16:43 +01:00 |
Clifford Wolf
|
bcc873b805
|
Fixed some visual studio warnings
|
2016-02-13 17:31:24 +01:00 |
Clifford Wolf
|
7bd329afa0
|
Support for more Verific primitives (patch I got per email)
|
2016-02-13 08:19:30 +01:00 |
Clifford Wolf
|
6a27cbe5b1
|
Bugfix in Verific front-end
|
2016-02-03 08:59:57 +01:00 |
Clifford Wolf
|
4a3e1ded1e
|
Updated verific build instructions
|
2016-02-02 19:50:17 +01:00 |
Clifford Wolf
|
ba407da187
|
Added addBufGate module method
|
2016-02-02 11:26:07 +01:00 |
Rick Altherr
|
34969d4140
|
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()
|
2016-01-31 09:20:16 -08:00 |
Clifford Wolf
|
5e90a78466
|
Various improvements in BLIF front-end
|
2015-12-20 13:12:24 +01:00 |
Clifford Wolf
|
4a697accd4
|
Fixed oom bug in ilang parser
|
2015-11-29 20:30:32 +01:00 |
Clifford Wolf
|
32f5ee117c
|
Fixed performance bug in ilang parser
|
2015-11-27 19:46:47 +01:00 |
Clifford Wolf
|
ab2d8e5c8c
|
Added PRIM_DLATCHRS support to verific front-end
|
2015-11-24 12:16:19 +01:00 |
Clifford Wolf
|
c86fbae3d1
|
Fixed handling of re-declarations of wires in tasks and functions
|
2015-11-23 17:09:57 +01:00 |
Clifford Wolf
|
415e0a1b90
|
Fixed performance bug in Verific importer
|
2015-11-16 12:38:56 +01:00 |
Clifford Wolf
|
b18f3a2974
|
Changes for Verific 3.16_484_32_151112
|
2015-11-12 19:28:14 +01:00 |
Clifford Wolf
|
7ae3d1b5a9
|
More bugfixes in handling of parameters in tasks and functions
|
2015-11-12 13:02:36 +01:00 |
Clifford Wolf
|
34f2b84fb6
|
Fixed handling of parameters and localparams in functions
|
2015-11-11 10:54:35 +01:00 |
Clifford Wolf
|
207736b4ee
|
Import more std:: stuff into Yosys namespace
|
2015-10-25 19:30:49 +01:00 |
Clifford Wolf
|
5308c1e02a
|
Fixed bug in verilog parser
|
2015-10-15 15:19:23 +02:00 |
Clifford Wolf
|
f13e387321
|
SystemVerilog also has assume(), added implicit -D FORMAL
|
2015-10-13 14:21:20 +02:00 |
Clifford Wolf
|
ba4cce9f19
|
Added support for "parameter" and "localparam" in global context
|
2015-10-07 14:59:08 +02:00 |
Clifford Wolf
|
e51dcc83d0
|
Fixed complexity of assigning to vectors in constant functions
|
2015-10-01 12:15:35 +02:00 |
Clifford Wolf
|
9caeadf797
|
Fixed detection of unconditional $readmem[hb]
|
2015-09-30 15:46:51 +02:00 |
Clifford Wolf
|
f9d7df0869
|
Bugfixes in $readmem[hb]
|
2015-09-25 13:49:48 +02:00 |
Clifford Wolf
|
b2544cfcf7
|
Fixed segfault in AstNode::asReal
|
2015-09-25 12:38:01 +02:00 |
Clifford Wolf
|
924d9d6e86
|
Added read-enable to memory model
|
2015-09-25 12:23:11 +02:00 |
Clifford Wolf
|
1b8cb9940e
|
Fixed AstNode::mkconst_bits() segfault on zero-sized constant
|
2015-09-24 11:21:20 +02:00 |
Clifford Wolf
|
e2e092b144
|
Added read_verilog -nodpi
|
2015-09-23 08:23:38 +02:00 |
Clifford Wolf
|
089c1e176f
|
Bugfix in handling of multi-dimensional memories
|
2015-09-23 07:56:17 +02:00 |
Clifford Wolf
|
559929e341
|
Warning for $display/$write outside initial block
|
2015-09-23 07:16:03 +02:00 |
Clifford Wolf
|
b845b77f86
|
Fixed support for $write system task
|
2015-09-23 07:10:56 +02:00 |
Clifford Wolf
|
a3a13cce32
|
Fixed detection of "task foo(bar);" syntax error
|
2015-09-22 21:34:21 +02:00 |
Clifford Wolf
|
6176f4d081
|
Fixed multi-level prefix resolving
|
2015-09-22 20:52:02 +02:00 |
Clifford Wolf
|
4b8200eb49
|
Fixed segfault on invalid verilog constant 1'b_
|
2015-09-22 08:13:09 +02:00 |
Andrew Zonenberg
|
c469f22144
|
Improvements to $display system task
|
2015-09-19 10:33:37 +02:00 |
Clifford Wolf
|
9db05d17fe
|
Added AST_INITIAL checks for $finish and $display
|
2015-09-18 09:50:57 +02:00 |
Andrew Zonenberg
|
7141f65533
|
Initial implementation of $display()
|
2015-09-18 09:36:46 +02:00 |
Andrew Zonenberg
|
e446e651cb
|
Initial implementation of $finish()
|
2015-09-18 09:30:25 +02:00 |
Clifford Wolf
|
b10ea0550d
|
gcc-4.6 build fixes
|
2015-09-01 12:51:23 +02:00 |
Clifford Wolf
|
eb38722e98
|
Fixed handling of memory read without address
|
2015-08-22 14:46:42 +02:00 |
Clifford Wolf
|
a7ab9172f9
|
Small corrections to const2ast warning messages
|
2015-08-17 16:22:53 +02:00 |
Florian Zeitz
|
0491042849
|
Check base-n literals only contain valid digits
|
2015-08-17 15:37:33 +02:00 |
Florian Zeitz
|
64ccbf8510
|
Warn on literals exceeding the specified bit width
|
2015-08-17 15:27:35 +02:00 |
Larry Doolittle
|
6c00704a5e
|
Another block of spelling fixes
Smaller this time
|
2015-08-14 23:27:05 +02:00 |
Larry Doolittle
|
022f570563
|
Keep gcc from complaining about uninitialized variables
|
2015-08-14 23:26:49 +02:00 |
Clifford Wolf
|
0350074819
|
Re-created command-reference-manual.tex, copied some doc fixes to online help
|
2015-08-14 11:27:19 +02:00 |
Clifford Wolf
|
84bf862f7c
|
Spell check (by Larry Doolittle)
|
2015-08-14 10:56:05 +02:00 |
Clifford Wolf
|
e4ef000b70
|
Adjust makefiles to work with out-of-tree builds
This is based on work done by Larry Doolittle
|
2015-08-12 15:04:44 +02:00 |
Clifford Wolf
|
45ee2ba3b8
|
Fixed handling of [a-fxz?] in decimal constants
|
2015-08-11 11:32:37 +02:00 |
Marcus Comstedt
|
c836faae3e
|
Add -noautowire option to verilog frontend
|
2015-08-01 12:16:54 +02:00 |
Clifford Wolf
|
8d6d5c30d9
|
Added WORDS parameter to $meminit
|
2015-07-31 10:40:09 +02:00 |
Clifford Wolf
|
4513ff1b85
|
Fixed nested mem2reg
|
2015-07-29 16:37:08 +02:00 |
Clifford Wolf
|
6c84341f22
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
Clifford Wolf
|
13983e8318
|
Fixed handling of parameters with reversed range
|
2015-06-08 14:03:06 +02:00 |
Clifford Wolf
|
99b8746d27
|
Fixed signedness of genvar expressions
|
2015-05-29 20:08:00 +02:00 |
Clifford Wolf
|
08a4af3cde
|
Improvements in BLIF front-end
|
2015-05-24 08:03:21 +02:00 |
Clifford Wolf
|
6061b7bd58
|
bugfix in blif front-end
|
2015-05-18 11:15:49 +02:00 |
Clifford Wolf
|
3ecb2bf067
|
Improved .latch support in BLIF front-end
|
2015-05-17 18:58:24 +02:00 |
Clifford Wolf
|
2cc4e75914
|
Added read_blif command
|
2015-05-17 15:25:03 +02:00 |
Clifford Wolf
|
e5116eeb77
|
Generalized blifparse API
|
2015-05-17 15:10:37 +02:00 |
Clifford Wolf
|
7dad017c9c
|
abc/blifparse files reorganization
|
2015-05-17 14:44:28 +02:00 |
Clifford Wolf
|
61512b6f41
|
Verific build fixes
|
2015-05-17 08:19:52 +02:00 |
Clifford Wolf
|
7ff802e199
|
Verilog front-end: define `BLACKBOX in -lib mode
|
2015-04-19 21:30:46 +02:00 |
Clifford Wolf
|
a923a63a89
|
Ignore celldefine directive in verilog front-end
|
2015-03-25 19:46:12 +01:00 |
Clifford Wolf
|
422794c584
|
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
|
2015-03-01 11:20:22 +01:00 |
Clifford Wolf
|
1f1deda888
|
Added non-std verilog assume() statement
|
2015-02-26 18:47:39 +01:00 |
Clifford Wolf
|
d5ce9a32ef
|
Added deep recursion warning to AST simplify
|
2015-02-20 10:33:20 +01:00 |
Clifford Wolf
|
dc1a0f06fc
|
Parser support for complex delay expressions
|
2015-02-20 10:21:36 +01:00 |
Clifford Wolf
|
e0e6d130cd
|
YosysJS stuff
|
2015-02-19 13:36:54 +01:00 |
Clifford Wolf
|
c2ba4fb2fd
|
Convert floating point cell parameters to strings
|
2015-02-18 23:35:23 +01:00 |
Clifford Wolf
|
e9368a1d7e
|
Various fixes for memories with offsets
|
2015-02-14 14:21:15 +01:00 |
Clifford Wolf
|
7f1a1759d7
|
Added "read_verilog -nomeminit" and "nomeminit" attribute
|
2015-02-14 11:21:12 +01:00 |
Clifford Wolf
|
a8e9d37c14
|
Creating $meminit cells in verilog front-end
|
2015-02-14 10:49:30 +01:00 |
Clifford Wolf
|
ef151b0b30
|
Fixed handling of "//" in filenames in verilog pre-processor
|
2015-02-14 08:41:03 +01:00 |
Clifford Wolf
|
cd919abdf1
|
Added AstNode::simplify() recursion counter
|
2015-02-13 12:33:12 +01:00 |
Clifford Wolf
|
4f68a77e3f
|
Improved read_verilog support for empty behavioral statements
|
2015-02-10 12:17:29 +01:00 |
Clifford Wolf
|
234a45a3d5
|
Ignore explicit assignments to constants in HDL code
|
2015-02-08 00:58:03 +01:00 |
Clifford Wolf
|
c8305e3a6d
|
Fixed a bug with autowire bit size
(removed leftover from when we tried to auto-size the wires)
|
2015-02-08 00:48:23 +01:00 |
Clifford Wolf
|
2a9ad48eb6
|
Added ENABLE_NDEBUG makefile options
|
2015-01-24 12:16:46 +01:00 |
Clifford Wolf
|
df9d096a7d
|
Ignoring more system task and functions
|
2015-01-15 13:08:19 +01:00 |
Clifford Wolf
|
a588a4a5c9
|
Fixed handling of "input foo; reg [0:0] foo;"
|
2015-01-15 12:53:12 +01:00 |
Clifford Wolf
|
8e8e791fb5
|
Consolidate "Blocking assignment to memory.." msgs for the same line
|
2015-01-15 12:41:52 +01:00 |
Fabio Utzig
|
fff6f00b3c
|
Enable bison to be customized
|
2015-01-08 09:56:20 -02:00 |
Clifford Wolf
|
1bd67d792e
|
Define YOSYS and SYNTHESIS in preproc
|
2015-01-02 17:11:54 +01:00 |
Clifford Wolf
|
eefe78be09
|
Fixed memory->start_offset handling
|
2015-01-01 12:56:01 +01:00 |
Clifford Wolf
|
0bb6b24c11
|
Added global yosys_celltypes
|
2014-12-29 14:30:33 +01:00 |
Clifford Wolf
|
90bc71dd90
|
dict/pool changes in ast
|
2014-12-29 03:11:50 +01:00 |
Clifford Wolf
|
137f35373f
|
Changed more code to dict<> and pool<>
|
2014-12-28 19:24:24 +01:00 |
Clifford Wolf
|
7751c491fb
|
Improved some warning messages
|
2014-12-27 03:40:27 +01:00 |
Clifford Wolf
|
12ca6538a4
|
Fixed mem2reg warning message
|
2014-12-27 03:26:30 +01:00 |
Clifford Wolf
|
a6c96b986b
|
Added Yosys::{dict,nodict,vector} container types
|
2014-12-26 10:53:21 +01:00 |
Clifford Wolf
|
edb3c9d0c4
|
Renamed extend() to extend_xx(), changed most users to extend_u0()
|
2014-12-24 09:51:17 +01:00 |
Clifford Wolf
|
1282a113da
|
Fixed supply0/supply1 with many wires
|
2014-12-11 13:56:20 +01:00 |
Clifford Wolf
|
76c83283c4
|
Fixed minor bug in parsing delays
|
2014-11-24 14:48:07 +01:00 |
Clifford Wolf
|
56c7d1e266
|
Fixed two minor bugs in constant parsing
|
2014-11-24 14:39:24 +01:00 |
Clifford Wolf
|
87333f3ae2
|
Added warning for use of 'z' constants in HDL
|
2014-11-14 19:59:50 +01:00 |
Clifford Wolf
|
4e5350b409
|
Fixed parsing of nested verilog concatenation and replicate
|
2014-11-12 19:10:35 +01:00 |
Clifford Wolf
|
fe829bdbdc
|
Added log_warning() API
|
2014-11-09 10:44:23 +01:00 |
Clifford Wolf
|
acf010d30d
|
Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions
|
2014-11-08 11:38:44 +01:00 |
Clifford Wolf
|
a21481b338
|
Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
|
2014-10-30 14:01:02 +01:00 |
Clifford Wolf
|
37aa2e02db
|
AST simplifier: optimize constant AST_CASE nodes before recursively descending
|
2014-10-29 08:29:51 +01:00 |
Clifford Wolf
|
f9c096eeda
|
Added support for task and function args in parentheses
|
2014-10-27 13:21:57 +01:00 |
Clifford Wolf
|
c4a2b3c1e9
|
Improvements in $readmem[bh] implementation
|
2014-10-26 23:29:36 +01:00 |
Clifford Wolf
|
70b2efdb05
|
Added support for $readmemh/$readmemb
|
2014-10-26 20:33:10 +01:00 |
Clifford Wolf
|
26cbe4a4e5
|
Fixed constant "cond ? string1 : string2" with strings of different size
|
2014-10-25 18:23:53 +02:00 |
Clifford Wolf
|
c5eb5e56b8
|
Re-introduced Yosys::readsome() helper function
(f.read() + f.gcount() made problems with lines > 16kB)
|
2014-10-23 10:58:36 +02:00 |
Clifford Wolf
|
750c615e7f
|
minor indenting corrections
|
2014-10-19 18:42:03 +02:00 |
Parviz Palangpour
|
de8adb8ec5
|
Builds on Mac 10.9.2 with LLVM 3.5.
|
2014-10-19 11:14:43 -05:00 |
Clifford Wolf
|
84ffe04075
|
Fixed various VS warnings
|
2014-10-18 15:20:38 +02:00 |
William Speirs
|
31267a1ae8
|
Header changes so it will compile on VS
|
2014-10-17 11:41:36 +02:00 |
William Speirs
|
fda52f05f2
|
Wrapped math in int constructor
|
2014-10-17 11:28:14 +02:00 |
Clifford Wolf
|
3838856a9e
|
Print "SystemVerilog" in "read_verilog -sv" log messages
|
2014-10-16 10:31:54 +02:00 |
Clifford Wolf
|
6b05a9e807
|
Fixed handling of invalid array access in mem2reg code
|
2014-10-16 00:44:23 +02:00 |
Clifford Wolf
|
f65e1c309f
|
Updated .gitignore file for ilang and verilog frontends
|
2014-10-15 01:14:38 +02:00 |
Clifford Wolf
|
c3e9922b5d
|
Replaced readsome() with read() and gcount()
|
2014-10-15 01:12:53 +02:00 |
William Speirs
|
fad0b0c506
|
Updated lexers & parsers to include prefixes
|
2014-10-15 00:48:19 +02:00 |
Clifford Wolf
|
0b9282a779
|
Added make_temp_{file,dir}() and remove_directory() APIs
|
2014-10-12 12:11:57 +02:00 |
Clifford Wolf
|
b1596bc0e7
|
Added run_command() api to replace system() and popen()
|
2014-10-12 10:57:15 +02:00 |
Clifford Wolf
|
35fbc0b35f
|
Do not the 'z' modifier in format string (another win32 fix)
|
2014-10-11 11:42:08 +02:00 |
Clifford Wolf
|
8263f6a74a
|
Fixed win32 troubles with f.readsome()
|
2014-10-11 11:36:22 +02:00 |
Clifford Wolf
|
0a651f112f
|
Disabled vhdl2verilog command for win32 builds
|
2014-10-11 10:46:19 +02:00 |
Clifford Wolf
|
bbd808072b
|
Added format __attribute__ to stringf()
|
2014-10-10 17:22:08 +02:00 |
Clifford Wolf
|
4569a747f8
|
Renamed SIZE() to GetSize() because of name collision on Win32
|
2014-10-10 17:07:24 +02:00 |
Clifford Wolf
|
f9a307a50b
|
namespace Yosys
|
2014-09-27 16:17:53 +02:00 |
Clifford Wolf
|
48b00dccea
|
Another $clog2 bugfix
|
2014-09-08 12:25:23 +02:00 |
Clifford Wolf
|
680eaaac41
|
Fixed $clog2 (off by one error)
|
2014-09-06 19:31:04 +02:00 |
Clifford Wolf
|
deff416ea7
|
Fixed assignment of out-of bounds array element
|
2014-09-06 17:58:27 +02:00 |
Ruben Undheim
|
79cbf9067c
|
Corrected spelling mistakes found by lintian
|
2014-09-06 08:47:06 +02:00 |
Clifford Wolf
|
8927aa6148
|
Removed $bu0 cell type
|
2014-09-04 02:07:52 +02:00 |
Clifford Wolf
|
58367cd87a
|
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
|
2014-08-23 15:14:58 +02:00 |
Clifford Wolf
|
19cff41eb4
|
Changed frontend-api from FILE to std::istream
|
2014-08-23 15:03:55 +02:00 |
Clifford Wolf
|
98442e019d
|
Added emscripten (emcc) support to build system and some build fixes
|
2014-08-22 16:20:22 +02:00 |
Clifford Wolf
|
e218f0eacf
|
Added support for non-standard <plugin>:<c_name> DPI syntax
|
2014-08-22 14:30:29 +02:00 |
Clifford Wolf
|
74af3a2b70
|
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
|
2014-08-22 14:22:09 +02:00 |
Clifford Wolf
|
ad146c2582
|
Fixed small memory leak in ast simplify
|
2014-08-21 17:33:40 +02:00 |
Clifford Wolf
|
6c5cafcd8b
|
Added support for DPI function with different names in C and Verilog
|
2014-08-21 17:22:04 +02:00 |
Clifford Wolf
|
085c8e873d
|
Added AstNode::asInt()
|
2014-08-21 17:11:51 +02:00 |
Clifford Wolf
|
490d7a5bf2
|
Fixed memory leak in DPI function calls
|
2014-08-21 13:09:47 +02:00 |
Clifford Wolf
|
7bfc4ae120
|
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
|
2014-08-21 12:43:51 +02:00 |
Clifford Wolf
|
38addd4c67
|
Added support for global tasks and functions
|
2014-08-21 12:42:28 +02:00 |
Clifford Wolf
|
640d9fc551
|
Added "via_celltype" attribute on task/func
|
2014-08-18 14:29:30 +02:00 |
Clifford Wolf
|
acb435b6cf
|
Added const folding of AST_CASE to AST simplifier
|
2014-08-18 00:02:30 +02:00 |
Clifford Wolf
|
64713647a9
|
Improved AST ProcessGenerator performance
|
2014-08-17 02:17:49 +02:00 |
Clifford Wolf
|
d491fd8c19
|
Use stackmap<> in AST ProcessGenerator
|
2014-08-17 00:57:24 +02:00 |
Clifford Wolf
|
7f734ecc09
|
Added module->uniquify()
|
2014-08-16 23:50:36 +02:00 |
Clifford Wolf
|
83e2698e10
|
AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
|
2014-08-16 19:31:59 +02:00 |
Clifford Wolf
|
f092b50148
|
Renamed $_INV_ cell type to $_NOT_
|
2014-08-15 14:11:40 +02:00 |
Clifford Wolf
|
c7afbd9d8e
|
Fixed bug in "read_verilog -ignore_redef"
|
2014-08-15 01:53:22 +02:00 |
Clifford Wolf
|
978a933b6a
|
Added RTLIL::SigSpec::to_sigbit_map()
|
2014-08-14 23:14:47 +02:00 |
Clifford Wolf
|
c83b990458
|
Changed the AST genWidthRTLIL subst interface to use a std::map
|
2014-08-14 23:02:07 +02:00 |
Clifford Wolf
|
6d56172c0d
|
Fixed line numbers when using here-doc macros
|
2014-08-14 22:26:30 +02:00 |
Clifford Wolf
|
85e3cc12ac
|
Fixed handling of task outputs
|
2014-08-14 22:26:10 +02:00 |
Clifford Wolf
|
1bf7a18fec
|
Added module->ports
|
2014-08-14 16:22:52 +02:00 |
Clifford Wolf
|
f53984795d
|
Added support for non-standard """ macro bodies
|
2014-08-13 13:03:38 +02:00 |
Clifford Wolf
|
593264e9ed
|
Fixed building verific bindings
|
2014-08-12 15:21:06 +02:00 |
Clifford Wolf
|
2dc3333734
|
Also allow "module foobar(input foo, output bar, ...);" syntax
|
2014-08-07 16:41:27 +02:00 |
Clifford Wolf
|
d259abbda2
|
Added AST_MULTIRANGE (arrays with more than 1 dimension)
|
2014-08-06 15:52:54 +02:00 |
Clifford Wolf
|
91dd87e60b
|
Improved scope resolution of local regs in Verilog+AST frontend
|
2014-08-05 12:15:53 +02:00 |
Clifford Wolf
|
0129d41efa
|
Fixed AST handling of variables declared inside a functions main block
|
2014-08-05 08:35:51 +02:00 |
Clifford Wolf
|
b5a3419ac2
|
Added support for non-standard "module mod_name(...);" syntax
|
2014-08-04 15:40:07 +02:00 |
Clifford Wolf
|
768eb846c4
|
More bugfixes related to new RTLIL::IdString
|
2014-08-02 18:14:21 +02:00 |
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
|
2014-08-02 13:19:57 +02:00 |
Clifford Wolf
|
14412e6c95
|
Preparations for RTLIL::IdString redesign: cleanup of existing code
|
2014-08-02 00:45:25 +02:00 |
Clifford Wolf
|
bd74ed7da4
|
Replaced sha1 implementation
|
2014-08-01 19:01:10 +02:00 |
Clifford Wolf
|
c6fd82c70b
|
Fixed build of verific bindings
|
2014-07-31 16:45:23 +02:00 |
Clifford Wolf
|
cdae8abe16
|
Renamed port access function on RTLIL::Cell, added param access functions
|
2014-07-31 16:38:54 +02:00 |
Clifford Wolf
|
e6d33513a5
|
Added module->design and cell->module, wire->module pointers
|
2014-07-31 14:11:39 +02:00 |
Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
7daad40ca4
|
Fixed counting verilog line numbers for "// synopsys translate_off" sections
|
2014-07-30 20:18:48 +02:00 |
Clifford Wolf
|
e605af8a49
|
Fixed Verilog pre-processor for files with no trailing newline
|
2014-07-29 20:14:25 +02:00 |
Clifford Wolf
|
397b00252d
|
Added $shift and $shiftx cell types (needed for correct part select behavior)
|
2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
48822e79a3
|
Removed left over debug code
|
2014-07-28 19:38:30 +02:00 |
Clifford Wolf
|
ec58965967
|
Fixed part selects of parameters
|
2014-07-28 19:24:28 +02:00 |
Clifford Wolf
|
a03297a7df
|
Set results of out-of-bounds static bit/part select to undef
|
2014-07-28 16:09:50 +02:00 |
Clifford Wolf
|
55521c085a
|
Fixed RTLIL code generator for part select of parameter
|
2014-07-28 15:31:19 +02:00 |
Clifford Wolf
|
0598bc8708
|
Fixed width detection for part selects
|
2014-07-28 15:19:34 +02:00 |
Clifford Wolf
|
27a872d1e7
|
Added support for "upto" wires to Verilog front- and back-end
|
2014-07-28 14:25:03 +02:00 |
Clifford Wolf
|
3c45277ee0
|
Added wire->upto flag for signals such as "wire [0:7] x;"
|
2014-07-28 12:12:13 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
ee65dea738
|
Fixed signdness detection of expressions with bit- and part-selects
|
2014-07-28 10:10:08 +02:00 |
Clifford Wolf
|
c4bdba78cb
|
Added proper Design->addModule interface
|
2014-07-27 21:12:09 +02:00 |
Clifford Wolf
|
7661ded8dd
|
Fixed verific bindings for new RTLIL api
|
2014-07-27 12:00:28 +02:00 |
Clifford Wolf
|
6b34215efd
|
Fixed ilang parser for new RTLIL API
|
2014-07-27 11:56:35 +02:00 |
Clifford Wolf
|
10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
|
2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
|
97a59851a6
|
Added RTLIL::Cell::has(portname)
|
2014-07-26 16:11:28 +02:00 |
Clifford Wolf
|
f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
309d64d46a
|
Fixed two memory leaks in ast simplify
|
2014-07-25 13:24:10 +02:00 |
Clifford Wolf
|
1488bc0c4f
|
Updated verific build/test instructions
|
2014-07-25 12:16:03 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
b17d6531c8
|
Added "make PRETTY=1"
|
2014-07-24 17:15:01 +02:00 |
Clifford Wolf
|
375aa71dfe
|
Various fixes in Verific frontend for new RTLIL API
|
2014-07-23 21:35:01 +02:00 |
Clifford Wolf
|
20a7965f61
|
Various small fixes (from gcc compiler warnings)
|
2014-07-23 20:45:27 +02:00 |
Clifford Wolf
|
c094c53de8
|
Removed RTLIL::SigSpec::optimize()
|
2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
ec923652e2
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
|
2014-07-23 09:52:55 +02:00 |
Clifford Wolf
|
a8d3a68971
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
|
2014-07-23 09:49:43 +02:00 |
Clifford Wolf
|
115dd959d9
|
SigSpec refactoring: More cleanups of old SigSpec use pattern
|
2014-07-22 23:50:21 +02:00 |
Clifford Wolf
|
28b3fd05fa
|
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
|
2014-07-22 20:58:44 +02:00 |
Clifford Wolf
|
7bffde6abd
|
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
|
2014-07-22 20:39:38 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
3b5f4ff39c
|
Fixed ilang parsing of process attributes
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
d6d0e08834
|
Fixed make rules for ilang parser
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
4147b55c23
|
Added "autoidx" statement to ilang file format
|
2014-07-21 15:15:18 +02:00 |
Clifford Wolf
|
361e0d62ff
|
Replaced depricated NEW_WIRE macro with module->addWire() calls
|
2014-07-21 12:42:02 +02:00 |
Clifford Wolf
|
1d88f1cf9f
|
Removed deprecated module->new_wire()
|
2014-07-21 12:35:06 +02:00 |
Clifford Wolf
|
9b183539af
|
Implemented dynamic bit-/part-select for memory writes
|
2014-07-17 16:49:23 +02:00 |
Clifford Wolf
|
5867f6bcdc
|
Added support for bit/part select to mem2reg rewriter
|
2014-07-17 13:49:32 +02:00 |
Clifford Wolf
|
6d69d4aaa8
|
Added support for constant bit- or part-select for memory writes
|
2014-07-17 13:13:21 +02:00 |
Clifford Wolf
|
b171a4c1bc
|
Added "inout" ports support to read_liberty
|
2014-07-16 18:12:46 +02:00 |
Clifford Wolf
|
5057935722
|
Set blackbox attribute in "read_liberty -lib"
|
2014-07-16 18:12:16 +02:00 |
Clifford Wolf
|
24f58e57f3
|
Fixed spelling of "direction" in read_liberty messages
|
2014-07-16 18:02:28 +02:00 |
Clifford Wolf
|
543551b80a
|
changes in verilog frontend for new $mem/$memwr WR_EN interface
|
2014-07-16 12:49:50 +02:00 |
Clifford Wolf
|
0f9ca49dc6
|
Added passing of various options to vhdl2verilog
|
2014-07-12 10:02:39 +02:00 |
Clifford Wolf
|
55a1b8dbac
|
Fixed processing of initial values for block-local variables
|
2014-07-11 13:05:53 +02:00 |
Clifford Wolf
|
ee8ad72fd9
|
fixed parsing of constant with comment between size and value
|
2014-07-02 06:27:04 +02:00 |
Clifford Wolf
|
076182c34e
|
Fixed handling of mixed real/int ternary expressions
|
2014-06-25 10:05:36 +02:00 |
Clifford Wolf
|
4fc43d1932
|
More found_real-related fixes to AstNode::detectSignWidthWorker
|
2014-06-24 15:08:48 +02:00 |
Clifford Wolf
|
65b2e9c064
|
fixed signdness detection for expressions with reals
|
2014-06-21 21:41:13 +02:00 |
Clifford Wolf
|
80e4594695
|
Added AstNode::MEM2REG_FL_CMPLX_LHS
|
2014-06-17 21:39:25 +02:00 |
Clifford Wolf
|
798ff88855
|
Improved handling of relational op of real values
|
2014-06-17 12:47:51 +02:00 |
Clifford Wolf
|
6c17d4f242
|
Improved ternary support for real values
|
2014-06-16 15:12:24 +02:00 |
Clifford Wolf
|
82bbd2f077
|
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
|
2014-06-16 15:05:37 +02:00 |
Clifford Wolf
|
0c4c79c4c6
|
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
|
2014-06-16 15:02:40 +02:00 |
Clifford Wolf
|
5bfe865cec
|
Added found_real feature to AstNode::detectSignWidth
|
2014-06-16 15:00:57 +02:00 |
Clifford Wolf
|
4d1df128fa
|
Improved AstNode::realAsConst for large numbers
|
2014-06-15 09:27:09 +02:00 |
Clifford Wolf
|
7f57bc8385
|
Improved parsing of large integer constants
|
2014-06-15 08:48:17 +02:00 |
Clifford Wolf
|
48dc6ab98d
|
Improved AstNode::asReal for large integers
|
2014-06-15 08:38:31 +02:00 |
Clifford Wolf
|
149fe83a8d
|
improved (fixed) conversion of real values to bit vectors
|
2014-06-14 21:00:51 +02:00 |
Clifford Wolf
|
d5765b5e14
|
Fixed relational operators for const real expressions
|
2014-06-14 19:33:58 +02:00 |
Clifford Wolf
|
f3b4a9dd24
|
Added support for math functions
|
2014-06-14 13:36:23 +02:00 |
Clifford Wolf
|
9bd7d5c468
|
Added handling of real-valued parameters/localparams
|
2014-06-14 12:00:47 +02:00 |
Clifford Wolf
|
fc7b6d172a
|
Implemented more real arithmetic
|
2014-06-14 11:27:05 +02:00 |
Clifford Wolf
|
442a8e2875
|
Implemented basic real arithmetic
|
2014-06-14 08:51:22 +02:00 |
Clifford Wolf
|
9dd16fa41c
|
Added real->int convertion in ast genrtlil
|
2014-06-14 07:44:19 +02:00 |
Clifford Wolf
|
7ef0da32cd
|
Added Verilog lexer and parser support for real values
|
2014-06-13 11:29:23 +02:00 |
Clifford Wolf
|
482d9208aa
|
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
|
2014-06-12 11:54:20 +02:00 |
Clifford Wolf
|
e275e8eef9
|
Add support for cell arrays
|
2014-06-07 11:48:50 +02:00 |
Clifford Wolf
|
0b1ce63a19
|
Added support for repeat stmt in const functions
|
2014-06-07 10:47:53 +02:00 |
Clifford Wolf
|
7c8a7b2131
|
further improved const function support
|
2014-06-07 00:02:05 +02:00 |
Clifford Wolf
|
5281562d0e
|
made the generate..endgenrate keywords optional
|
2014-06-06 23:05:01 +02:00 |
Clifford Wolf
|
76da2fe172
|
improved const function support
|
2014-06-06 22:55:02 +02:00 |
Clifford Wolf
|
5c10d2ee36
|
fix functions with no block (but single statement, loop, etc.)
|
2014-06-06 21:29:23 +02:00 |
Clifford Wolf
|
ab54ce17c8
|
improved ast simplify of const functions
|
2014-06-06 17:40:45 +02:00 |
Clifford Wolf
|
b5cd7a0179
|
added while and repeat support to verilog parser
|
2014-06-06 17:40:04 +02:00 |
Clifford Wolf
|
f9c1cd5edb
|
Improved error message for options after front-end filename arguments
|
2014-06-04 09:10:50 +02:00 |
Johann Glaser
|
63dfbb18cf
|
new flags -ignore_miss_func and -ignore_miss_dir for read_liberty
|
2014-05-28 16:50:13 +02:00 |
Clifford Wolf
|
7188542155
|
Fixed clang -Wdeprecated-register warnings
|
2014-04-20 14:28:23 +02:00 |
Clifford Wolf
|
a1be4816d6
|
Replaced depricated %name-prefix= bison directive
|
2014-04-20 14:22:11 +02:00 |
Clifford Wolf
|
a3b9692a68
|
Fixed mapping of Verific WIDE_DFFRS operator
|
2014-03-20 13:40:01 +01:00 |
Clifford Wolf
|
470c2455e4
|
Fixed mapping of Verific FADD primitive with unconnected outputs
|
2014-03-20 13:26:52 +01:00 |
Clifford Wolf
|
cdf1257565
|
Progress in Verific bindings
|
2014-03-17 14:43:16 +01:00 |
Clifford Wolf
|
0b0dcfda7d
|
Progress in Verific bindings
|
2014-03-17 02:43:53 +01:00 |
Clifford Wolf
|
a67cd2d4a2
|
Progress in Verific bindings
|
2014-03-17 01:56:00 +01:00 |
Clifford Wolf
|
acda74c12c
|
Added support for memories to verific bindings
|
2014-03-16 17:05:05 +01:00 |
Clifford Wolf
|
7545510edc
|
Use Verific Net::{IsGnd,IsPwr} API in Verific bindings
|
2014-03-16 16:06:03 +01:00 |
Clifford Wolf
|
0ebee4c8e7
|
Progress in Verific bindings
|
2014-03-15 22:51:12 +01:00 |
Clifford Wolf
|
fc2c821407
|
Progress in Verific bindings
|
2014-03-15 15:31:54 +01:00 |
Clifford Wolf
|
1d00ad9d4d
|
Progress in Verific bindings
|
2014-03-15 14:36:11 +01:00 |
Clifford Wolf
|
e37d672ae7
|
Progress in Verific bindings
|
2014-03-14 16:40:25 +01:00 |
Clifford Wolf
|
0ac915a757
|
Progress in Verific bindings
|
2014-03-14 11:46:13 +01:00 |
Clifford Wolf
|
9a1accf692
|
Progress in Verific bindings
|
2014-03-13 18:21:00 +01:00 |
Clifford Wolf
|
6a53bc7b27
|
Copy Verific vdbs files to Yosys "share" data directory
|
2014-03-13 17:34:31 +01:00 |
Clifford Wolf
|
7a1ac11203
|
Added test_navre.ys for verific frontend
|
2014-03-13 13:12:06 +01:00 |
Clifford Wolf
|
fad8558eb5
|
Merged OSX fixes from Siesh1oo with some modifications
|
2014-03-13 12:48:10 +01:00 |
Clifford Wolf
|
91704a7853
|
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
|
2014-03-11 14:24:24 +01:00 |
Clifford Wolf
|
9992026a8d
|
Added support for `line compiler directive
|
2014-03-11 14:06:57 +01:00 |
Clifford Wolf
|
5a15539c9b
|
Improved verific command (added support for some operators)
|
2014-03-10 12:06:57 +01:00 |
Clifford Wolf
|
c71791a1ff
|
Improvements in verific command
|
2014-03-10 03:03:08 +01:00 |
Clifford Wolf
|
8d06f9f2fe
|
Added "verific" command
|
2014-03-09 20:40:04 +01:00 |
Clifford Wolf
|
620d51d9f7
|
Bugfix in ilang frontend autoidx recovery
|
2014-03-07 17:19:14 +01:00 |
Clifford Wolf
|
4d07f88258
|
Fixed gcc compiler warning
|
2014-03-06 16:37:19 +01:00 |
Clifford Wolf
|
09805ee9ec
|
Include id2ast pointers when dumping AST
|
2014-03-05 19:56:31 +01:00 |
Clifford Wolf
|
d6a01fe412
|
Fixed merging of compatible wire decls in AST frontend
|
2014-03-05 19:55:58 +01:00 |
Clifford Wolf
|
de7bd12004
|
Bugfix in recursive AST simplification
|
2014-03-05 19:45:33 +01:00 |
Clifford Wolf
|
ef90236a5d
|
Fixed vhdl2verilog temp dir name
|
2014-03-01 17:48:15 +01:00 |
Clifford Wolf
|
04999f4af0
|
Fixed vhdl2verilog help message
|
2014-03-01 17:47:19 +01:00 |
Clifford Wolf
|
ae5032af84
|
Fixed bit-extending in $mux argument (use $bu0 instead of $pos)
|
2014-02-26 21:32:19 +01:00 |
Clifford Wolf
|
6bc94b7eb2
|
Don't blow up constants unneccessarily in Verilog frontend
|
2014-02-24 12:41:25 +01:00 |
Clifford Wolf
|
f8c9143b2b
|
Fixed bug in generation of undefs for $memwr MUXes
|
2014-02-22 17:08:00 +01:00 |
Clifford Wolf
|
0a60f95224
|
Added vhdl2verilog
|
2014-02-21 18:59:49 +01:00 |
Clifford Wolf
|
4bd25edcd4
|
Cleanups in handling of read_verilog -defer and -icells
|
2014-02-20 19:12:32 +01:00 |
Clifford Wolf
|
02e6f2c5be
|
Added Verilog support for "`default_nettype none"
|
2014-02-17 14:28:52 +01:00 |
Clifford Wolf
|
7d7e068dd1
|
Added a warning note about error reporting to read_verilog help message
|
2014-02-16 20:20:25 +01:00 |
Clifford Wolf
|
7ac524e8e8
|
Improved support for constant functions
|
2014-02-16 13:16:38 +01:00 |
Clifford Wolf
|
118517ca5a
|
Added ff and latch support to read_liberty
|
2014-02-15 19:44:19 +01:00 |
Clifford Wolf
|
96b1ebc8dc
|
Bugfix in expression parser of read_liberty
|
2014-02-15 19:36:09 +01:00 |
Clifford Wolf
|
5e39e6ece2
|
Correctly convert constants to RTLIL (fixed undef handling)
|
2014-02-15 15:42:10 +01:00 |
Clifford Wolf
|
4440610d3f
|
Added liberty frontend
|
2014-02-15 12:57:28 +01:00 |
Clifford Wolf
|
45d2b6ffce
|
Be more conservative with new const-function code
|
2014-02-14 20:45:30 +01:00 |
Clifford Wolf
|
e8af3def7f
|
Added support for FOR loops in function calls in parameters
|
2014-02-14 20:33:22 +01:00 |
Clifford Wolf
|
534c1a5dd0
|
Created basic support for function calls in parameter values
|
2014-02-14 19:56:44 +01:00 |
Clifford Wolf
|
cd9e8741a7
|
Implemented read_verilog -defer
|
2014-02-13 13:59:13 +01:00 |
Clifford Wolf
|
007bdff55d
|
Added support for functions returning integer
|
2014-02-12 23:29:54 +01:00 |
Clifford Wolf
|
0defc86519
|
renamed ilang "scope error" to "ilang error"
|
2014-02-11 19:17:07 +01:00 |
Clifford Wolf
|
fb186e6299
|
Improved ilang parser error messages
|
2014-02-09 15:35:31 +01:00 |
Clifford Wolf
|
f4f230d7cc
|
Fixed gcc compiler warnings with release build
|
2014-02-06 22:49:14 +01:00 |
Clifford Wolf
|
aa8e754ae5
|
Added read_verilog -setattr
|
2014-02-05 11:22:10 +01:00 |
Clifford Wolf
|
d267bcde4e
|
Fixed bug in sequential sat proofs and improved handling of asserts
|
2014-02-04 12:46:16 +01:00 |
Clifford Wolf
|
a6750b3753
|
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
|
2014-02-03 13:01:45 +01:00 |
Clifford Wolf
|
cdd6e11af5
|
Added support for blanks after -I and -D in read_verilog
|
2014-02-02 13:06:21 +01:00 |
Clifford Wolf
|
af325bf206
|
Fixed comment/eol parsing in ilang frontend
|
2014-02-01 17:28:02 +01:00 |
Clifford Wolf
|
d06258f74f
|
Added constant size expression support of sized constants
|
2014-02-01 13:50:23 +01:00 |
Clifford Wolf
|
4df7e03ec9
|
Bugfix in name resolution with generate blocks
|
2014-01-30 15:01:28 +01:00 |
Clifford Wolf
|
375c4dddc1
|
Added read_verilog -icells option
|
2014-01-29 00:59:28 +01:00 |
Clifford Wolf
|
0b47d907d3
|
Fixed handling of unsized constants in verilog frontend
|
2014-01-24 15:05:24 +01:00 |
Clifford Wolf
|
88fbdd4916
|
Fixed algorithmic complexity of AST simplification of long expressions
|
2014-01-20 20:25:20 +01:00 |
Clifford Wolf
|
1e67099b77
|
Added $assert cell
|
2014-01-19 14:03:40 +01:00 |
Clifford Wolf
|
9a1eb45c75
|
Added Verilog parser support for asserts
|
2014-01-19 04:18:22 +01:00 |
Clifford Wolf
|
13359d65ba
|
Fixed parsing of verilog macros at end of line
|
2014-01-18 19:22:20 +01:00 |
Clifford Wolf
|
6170cfe9cd
|
Added verilog_defaults command
|
2014-01-17 17:22:29 +01:00 |
Clifford Wolf
|
a3d94bf888
|
Fixed typo in frontends/ast/simplify.cc
|
2014-01-12 21:04:42 +01:00 |
Clifford Wolf
|
8f11eaaca6
|
Added updating of RTLIL::autoidx to ilang frontend
|
2014-01-03 17:51:05 +01:00 |
Clifford Wolf
|
fb2bf934dc
|
Added correct handling of $memwr priority
|
2014-01-03 00:22:17 +01:00 |
Clifford Wolf
|
364f277afb
|
Fixed a stupid access after delete bug
|
2013-12-29 20:18:22 +01:00 |
Clifford Wolf
|
1dcbba1abf
|
Fixed parsing of non-arg macro calls followed by "("
|
2013-12-27 16:25:27 +01:00 |
Clifford Wolf
|
72026a934e
|
Fixed parsing of macros with no arguments and expansion text starting with "("
|
2013-12-27 15:05:52 +01:00 |
Clifford Wolf
|
369bf81a70
|
Added support for non-const === and !== (for miter circuits)
|
2013-12-27 14:20:15 +01:00 |
Clifford Wolf
|
ecc30255ba
|
Added proper === and !== support in constant expressions
|
2013-12-27 13:50:08 +01:00 |
Clifford Wolf
|
fbd06a1afc
|
Added elsif preproc support
|
2013-12-18 13:41:36 +01:00 |
Clifford Wolf
|
921064c200
|
Added support for macro arguments
|
2013-12-18 13:21:02 +01:00 |
Clifford Wolf
|
891e4b5b0d
|
Keep strings as strings in const ternary and concat
|
2013-12-05 13:26:17 +01:00 |
Clifford Wolf
|
e935bb6eda
|
Added const folding support for $signed and $unsigned
|
2013-12-05 13:09:41 +01:00 |
Clifford Wolf
|
5c39948ead
|
Added AstNode::mkconst_str API
|
2013-12-05 12:53:49 +01:00 |
Clifford Wolf
|
853538d78b
|
Fixed generate-for (and disabled double warning for auto-wire)
|
2013-12-04 21:33:00 +01:00 |
Clifford Wolf
|
3c220e0b32
|
Added support for $clog2 system function
|
2013-12-04 21:19:54 +01:00 |
Clifford Wolf
|
4a4a3fc337
|
Various improvements in support for generate statements
|
2013-12-04 21:06:54 +01:00 |
Clifford Wolf
|
f4b46ed31e
|
Replaced signed_parameters API with CONST_FLAG_SIGNED
|
2013-12-04 14:24:44 +01:00 |
Clifford Wolf
|
93a70959f3
|
Replaced RTLIL::Const::str with generic decoder method
|
2013-12-04 14:14:05 +01:00 |
Clifford Wolf
|
507c63d112
|
Added support for local regs in named blocks
|
2013-12-04 09:10:16 +01:00 |
Clifford Wolf
|
10aa08dca1
|
Fixed temp net name generation in rtlil process generator for abbreviated name matching
|
2013-11-28 21:47:08 +01:00 |
Clifford Wolf
|
0e52f3fa01
|
Added "src" attribute to processes
|
2013-11-28 17:37:50 +01:00 |
Clifford Wolf
|
8dafecd34d
|
Added module->avail_parameters (for advanced techmap features)
|
2013-11-24 20:29:07 +01:00 |
Clifford Wolf
|
7d9a90396d
|
Added verilog frontend -ignore_redef option
|
2013-11-24 19:57:42 +01:00 |
Clifford Wolf
|
019b301541
|
Early wire/reg/parameter width calculation in ast/simplify
|
2013-11-24 19:40:23 +01:00 |
Clifford Wolf
|
0ef22c7609
|
Added support for signed parameters in ilang
|
2013-11-24 17:37:27 +01:00 |
Clifford Wolf
|
f71e27dbf1
|
Remove auto_wire framework (smarter than the verilog standard)
|
2013-11-24 17:29:11 +01:00 |
Clifford Wolf
|
609caa23b5
|
Implemented correct handling of signed module parameters
|
2013-11-24 17:17:21 +01:00 |
Clifford Wolf
|
1de12e1efc
|
Improved handling of initialized registers
|
2013-11-23 16:26:59 +01:00 |
Clifford Wolf
|
295e352ba6
|
Renamed "placeholder" to "blackbox"
|
2013-11-22 15:01:12 +01:00 |
Clifford Wolf
|
a362fd81ae
|
Fixed O(n^2) performance bug in verilog preprocessor
|
2013-11-22 14:08:43 +01:00 |
Clifford Wolf
|
e4429c480e
|
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
|
2013-11-22 12:46:02 +01:00 |
Clifford Wolf
|
95c94a02fc
|
Fixed async proc detection in mem2reg
|
2013-11-21 21:26:56 +01:00 |
Clifford Wolf
|
09471846c5
|
Major improvements in mem2reg and added "init" sync rules
|
2013-11-21 13:49:00 +01:00 |
Clifford Wolf
|
08ceb3729e
|
Fixed ilang parser: memory width
|
2013-11-20 19:55:52 +01:00 |
Clifford Wolf
|
65ad556f3d
|
Another name resolution bugfix for generate blocks
|
2013-11-20 13:57:40 +01:00 |
Clifford Wolf
|
92035fb38e
|
Implemented indexed part selects
|
2013-11-20 13:05:27 +01:00 |
Clifford Wolf
|
c4c299eb5a
|
Do not allow memory bit select on the left side of an assignment
|
2013-11-20 12:18:46 +01:00 |
Clifford Wolf
|
0f04738f40
|
Added "synthesis" in (synopsys|synthesis) comment support
|
2013-11-20 11:44:09 +01:00 |
Clifford Wolf
|
ac2be2d892
|
Fixed name resolution of local tasks and functions in generate block
|
2013-11-20 11:05:58 +01:00 |
Clifford Wolf
|
19dba2561e
|
Implemented part/bit select on memory read
|
2013-11-20 10:51:32 +01:00 |
Clifford Wolf
|
e340532ce5
|
Added init= attribute for fpga-style reset values
|
2013-11-20 01:49:37 +01:00 |
Clifford Wolf
|
0dfdbd991a
|
Fixed parsing of module arguments when one type is used for many args
|
2013-11-19 20:35:31 +01:00 |
Clifford Wolf
|
4f2edcf2f9
|
Fixed two bugs in mem2reg functionality in AST frontend
|
2013-11-18 19:55:12 +01:00 |
Clifford Wolf
|
79910a5547
|
Added dumping of attributes in AST frontend
|
2013-11-18 19:54:36 +01:00 |
Clifford Wolf
|
2a25e3bca3
|
Fixed parsing of default cases when not last case
|
2013-11-18 16:10:50 +01:00 |
Clifford Wolf
|
de03184150
|
Fixed mem2reg for reg usage outside always block
|
2013-11-18 12:35:41 +01:00 |
Clifford Wolf
|
63060dcd2e
|
Fixed parsing of "parameter integer"
|
2013-11-13 15:30:23 +01:00 |
Clifford Wolf
|
e5b974fa2a
|
Cleanups and bugfixes in response to new internal cell checker
|
2013-11-11 00:39:45 +01:00 |
Clifford Wolf
|
378cc509cd
|
Call internal checker more often
|
2013-11-10 23:24:21 +01:00 |
Clifford Wolf
|
259cc1391e
|
More undef-propagation related fixes
|
2013-11-08 11:40:36 +01:00 |
Clifford Wolf
|
9f49d538e1
|
Fixed handling of different signedness in power operands
|
2013-11-08 11:06:11 +01:00 |
Clifford Wolf
|
4abc8e695a
|
Implemented const folding of ternary op with undef select
|
2013-11-08 04:44:09 +01:00 |
Clifford Wolf
|
fc6dc0d7b8
|
Fixed handling of power operator
|
2013-11-07 22:20:00 +01:00 |
Clifford Wolf
|
d7cb62ac96
|
Fixed more extend vs. extend_u0 issues
|
2013-11-07 19:20:20 +01:00 |
Clifford Wolf
|
02f4f89fdb
|
Disabled const folding of ternary op when select is undef
|
2013-11-07 18:18:16 +01:00 |
Clifford Wolf
|
947bd9b96b
|
Renamed extend_un0() to extend_u0() and use it in genrtlil
|
2013-11-07 18:17:10 +01:00 |
Clifford Wolf
|
ed4bcd52e5
|
Fixed sign handling in constants
|
2013-11-07 14:53:10 +01:00 |
Clifford Wolf
|
83a8b8b5ca
|
Fixed const folding in corner cases with parameters
|
2013-11-07 14:08:53 +01:00 |
Clifford Wolf
|
b52bf379b9
|
Fixed width detection for replicate operator
|
2013-11-07 12:43:04 +01:00 |
Clifford Wolf
|
536621a98b
|
Fixed at_zero evaluation of dynamic ranges
|
2013-11-07 11:25:19 +01:00 |
Clifford Wolf
|
f050c40519
|
Various fixes for correct parameter support
|
2013-11-07 10:02:11 +01:00 |
Clifford Wolf
|
160adccca2
|
Fixed the fix for propagation of width hints for $signed() and $unsigned()
|
2013-11-07 03:01:28 +01:00 |
Clifford Wolf
|
7fe13faefa
|
Fixed propagation of width hints for $signed() and $unsigned()
|
2013-11-06 22:41:21 +01:00 |
Clifford Wolf
|
baeca48a24
|
Additional fixes for undef propagation in concat and replicate ops
|
2013-11-06 21:16:54 +01:00 |
Clifford Wolf
|
6fcbc79b5c
|
Improved width extension with regard to undef propagation
|
2013-11-06 21:05:11 +01:00 |
Clifford Wolf
|
f2786df146
|
Another fix for early width and sign detection in ast simplifier
|
2013-11-04 21:29:36 +01:00 |
Clifford Wolf
|
d38c67f53d
|
Fixed const folding of ternary operator
|
2013-11-04 16:46:14 +01:00 |
Clifford Wolf
|
8d226da694
|
Use proper bit width ans sign extension for const folding
|
2013-11-04 15:37:09 +01:00 |
Clifford Wolf
|
1325514d33
|
Fixes for early width and sign detection in ast simplifier
|
2013-11-04 08:28:13 +01:00 |
Clifford Wolf
|
472117d532
|
further improved early width and sign detection in ast simplifier
|
2013-11-04 06:04:42 +01:00 |
Clifford Wolf
|
d2b083f5cb
|
Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
|
2013-11-03 18:56:45 +01:00 |
Clifford Wolf
|
ada80545fa
|
Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
|
2013-11-02 21:13:01 +01:00 |
Clifford Wolf
|
943329c1dc
|
Various ast changes for early expression width detection (prep for constfold fixes)
|
2013-11-02 13:00:17 +01:00 |
Clifford Wolf
|
23cf23418c
|
Fixed handling of boolean attributes (frontends)
|
2013-10-24 11:20:13 +02:00 |
Clifford Wolf
|
eae43e2db4
|
Fixed handling of boolean attributes (kernel)
|
2013-10-24 10:59:27 +02:00 |
Clifford Wolf
|
77726fb5fe
|
Fixed parsing of value-less attributes in ilang
|
2013-10-23 18:38:31 +02:00 |
Johann Glaser
|
f352205635
|
fixed Verilog parser filename and line numbering issue with include files
|
2013-08-21 09:20:59 +02:00 |
Johann Glaser
|
a99c224157
|
Added support for include directories with the new '-I' argument of the
'read_verilog' command
|
2013-08-20 15:48:16 +02:00 |
Johann Glaser
|
6c4cbc03c2
|
Added support for notif0/notif1 primitives
|
2013-08-20 11:23:59 +02:00 |
Clifford Wolf
|
0003743432
|
Fixed width and sign detection for ** operator
|
2013-08-19 20:58:01 +02:00 |
Clifford Wolf
|
8656b1c08f
|
Added support for bufif0/bufif1 primitives
|
2013-08-19 19:50:04 +02:00 |
Clifford Wolf
|
4214561890
|
Improved ast dumping (ast/verilog frontend)
|
2013-08-19 19:49:14 +02:00 |
Clifford Wolf
|
759852914d
|
Added support for "2**n" shifter encoding
|
2013-08-12 14:47:50 +02:00 |
Clifford Wolf
|
c8763301b4
|
Added $div and $mod technology mapping
|
2013-08-09 17:09:24 +02:00 |
Clifford Wolf
|
0f38008ed3
|
Added "design" command (-reset, -save, -load)
|
2013-07-27 14:27:51 +02:00 |
Clifford Wolf
|
3650fd7fbe
|
More fixes in ternary op sign handling
|
2013-07-12 13:13:04 +02:00 |
Clifford Wolf
|
ded769c98c
|
Fixed sign handling in ternary operator
|
2013-07-12 01:15:37 +02:00 |
Clifford Wolf
|
b380c8c790
|
Another vloghammer related bugfix
|
2013-07-11 19:24:59 +02:00 |
Clifford Wolf
|
ed62fcdbe2
|
Fixed sign propagation in bit-wise operators
|
2013-07-09 23:53:55 +02:00 |
Clifford Wolf
|
5dab327b30
|
More fixes in ast expression sign/width handling
|
2013-07-09 23:41:43 +02:00 |
Clifford Wolf
|
00a6c1d9a5
|
Major redesign of expr width/sign detecion (verilog/ast frontend)
|
2013-07-09 14:31:57 +02:00 |
Clifford Wolf
|
e8da3ea7b6
|
Fixed another bug found using vloghammer
|
2013-07-07 16:49:30 +02:00 |
Clifford Wolf
|
eff68560a2
|
Fixed AST_CONSTANT node generation
|
2013-07-07 15:40:26 +02:00 |
Clifford Wolf
|
56432a920f
|
Added defparam support to Verilog/AST frontend
|
2013-07-04 14:12:33 +02:00 |
Clifford Wolf
|
0c6ffc4c65
|
More fixes for bugs found using xsthammer
|
2013-06-13 11:18:45 +02:00 |
Clifford Wolf
|
4b311b7b99
|
Further improved and extended xsthammer
|
2013-06-11 19:49:35 +02:00 |
Clifford Wolf
|
a5c30183b5
|
Sign-extension related fixes in SatGen and AST frontend
|
2013-06-10 17:10:06 +02:00 |
Clifford Wolf
|
59dd02baa2
|
Fixes and improvements in AST const folding
|
2013-06-10 13:56:03 +02:00 |
Clifford Wolf
|
db98a18edb
|
Enabled AST/Verilog front-end optimizations per default
|
2013-06-10 13:19:04 +02:00 |
Clifford Wolf
|
46fbe9d262
|
Added SAT generator and simple sat_solve command
|
2013-06-07 13:59:13 +02:00 |
Clifford Wolf
|
ed0e2f7a6f
|
Added log_assert() api
|
2013-05-24 14:38:36 +02:00 |
Clifford Wolf
|
375f83c5ec
|
Fixed memory leak in ilang frontend
|
2013-05-23 12:55:59 +02:00 |
Johann Glaser
|
10a195c0a1
|
added option '-Dname[=definition]' to command 'read_verilog'
|
2013-05-19 17:07:52 +02:00 |
Clifford Wolf
|
c5ee2b306a
|
Merge branch 'bugfix'
|
2013-05-16 16:44:45 +02:00 |
Clifford Wolf
|
6cc8e848b6
|
Fixed synthesis of functions in latched blocks
|
2013-05-16 16:44:06 +02:00 |
Clifford Wolf
|
b56e06d2f5
|
Added support for verilog === operator
|
2013-05-07 14:35:40 +02:00 |
Clifford Wolf
|
8f2d90de4f
|
Fixed handling of positional module parameters
|
2013-04-26 14:40:25 +02:00 |
Clifford Wolf
|
453a29c9f6
|
Only use sha1 checksums for names of parametric modules when the verbose form is to long
|
2013-04-26 13:13:58 +02:00 |
Clifford Wolf
|
e0c408cb4a
|
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
|
2013-04-13 21:19:10 +02:00 |
Clifford Wolf
|
f1a2fd966f
|
Now only use value from "initial" when no matching "always" block is found
|
2013-03-31 11:51:12 +02:00 |
Clifford Wolf
|
161565be10
|
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
|
2013-03-31 11:19:11 +02:00 |
Clifford Wolf
|
7bfc7b61a8
|
Implemented proper handling of stub placeholder modules
|
2013-03-28 09:20:10 +01:00 |
Clifford Wolf
|
7a99349de4
|
Improvements and bugfixes for generate blocks with local signals
|
2013-03-26 11:31:34 +01:00 |
Clifford Wolf
|
6a382f2aba
|
Fixed handling of unconditional generate blocks
|
2013-03-26 09:44:54 +01:00 |
Clifford Wolf
|
227520f94d
|
Added nosync attribute and some async reset related fixes
|
2013-03-25 17:13:14 +01:00 |
Clifford Wolf
|
df9753d398
|
Added mem2reg option to verilog frontend
|
2013-03-24 11:13:32 +01:00 |
Clifford Wolf
|
3a5244e913
|
Another fix in mem2reg ast simplify logic
|
2013-03-24 10:42:08 +01:00 |
Clifford Wolf
|
bb3357c027
|
Improved mem2reg handling in ast simplifier
|
2013-03-24 09:27:01 +01:00 |
Clifford Wolf
|
e45d1c8865
|
Tiny fixes to verilog parser
|
2013-03-23 18:54:31 +01:00 |
Clifford Wolf
|
8a6b0a3520
|
Added help messages to ilang and verilog frontends
|
2013-03-01 08:03:00 +01:00 |
Clifford Wolf
|
a321a5c412
|
Moved stand-alone libs to libs/ directory and added libs/subcircuit
|
2013-02-27 09:32:19 +01:00 |
Clifford Wolf
|
4f0c2862a0
|
Added support for verilog genblock[index].member syntax
|
2013-02-26 13:18:22 +01:00 |
Clifford Wolf
|
6d1502b948
|
Added support for "always @(*)"
|
2013-01-16 17:32:11 +01:00 |
Clifford Wolf
|
6543917fb8
|
added .gitignore files
|
2013-01-05 11:19:11 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |