mirror of https://github.com/YosysHQ/yosys.git
Added read_verilog -setattr
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@ -106,6 +106,9 @@ struct VerilogFrontend : public Frontend {
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message.)\n");
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log("\n");
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log(" -setattr <attribute_name>\n");
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log(" set the specified attribute (to the value 1) on all loaded modules\n");
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log("\n");
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log(" -Dname[=definition]\n");
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log(" define the preprocessor symbol 'name' and set its optional value\n");
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log(" 'definition'\n");
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@ -134,6 +137,7 @@ struct VerilogFrontend : public Frontend {
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bool flag_ignore_redef = false;
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std::map<std::string, std::string> defines_map;
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std::list<std::string> include_dirs;
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std::list<std::string> attributes;
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frontend_verilog_yydebug = false;
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log_header("Executing Verilog-2005 frontend.\n");
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@ -195,6 +199,10 @@ struct VerilogFrontend : public Frontend {
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flag_ignore_redef = true;
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continue;
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}
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if (arg == "-setattr" && argidx+1 < args.size()) {
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attributes.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (arg == "-D" && argidx+1 < args.size()) {
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std::string name = args[++argidx], value;
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size_t equal = name.find('=', 2);
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@ -249,6 +257,13 @@ struct VerilogFrontend : public Frontend {
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frontend_verilog_yyparse();
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frontend_verilog_yylex_destroy();
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for (auto &child : current_ast->children) {
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log_assert(child->type == AST::AST_MODULE);
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for (auto &attr : attributes)
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if (child->attributes.count(attr) == 0)
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child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
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}
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef);
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if (!flag_nopp)
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