mirror of https://github.com/YosysHQ/yosys.git
Fixed AST_CONSTANT node generation
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@ -661,7 +661,7 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe
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node->integer |= (node->bits.back() == RTLIL::S1) << i;
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}
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node->range_valid = true;
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node->range_left = node->bits.size();
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node->range_left = node->bits.size()-1;
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node->range_right = 0;
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return node;
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}
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