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Add a paragraph about pre-defined macros to read_verilog help message

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Clifford Wolf 2017-07-21 14:34:53 +02:00
parent 3a8f6f0f51
commit 26766da343
1 changed files with 4 additions and 0 deletions
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4
frontends/verilog/verilog_frontend.cc
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@ -168,6 +168,10 @@ struct VerilogFrontend : public Frontend {
log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
log("the syntax of the code, rather than to rely on read_verilog for that.\n");
log("\n");
log("Depending on if read_verilog is run in -formal mode, either the macro\n");
log("SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog\n");
log("always defines the macro YOSYS.\n");
log("\n");
log("See the Yosys README file for a list of non-standard Verilog features\n");
log("supported by the Yosys Verilog front-end.\n");
log("\n");