mirror of https://github.com/YosysHQ/yosys.git
Added real->int convertion in ast genrtlil
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@ -602,6 +602,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
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sign_hint = false;
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break;
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case AST_REALVALUE:
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width_hint = std::max(width_hint, 32);
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break;
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case AST_IDENTIFIER:
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id_ast = id2ast;
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if (id_ast == NULL && current_scope.count(str))
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@ -909,6 +913,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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return RTLIL::SigSpec(bitsAsConst());
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}
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case AST_REALVALUE:
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{
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int intvalue = round(realvalue);
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log("Warning: converting real value %e to integer %d at %s:%d.\n",
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realvalue, intvalue, filename.c_str(), linenum);
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return RTLIL::SigSpec(intvalue);
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}
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// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
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// for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
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// shifter cell is created and the output signal of this cell is returned
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