riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed handling of unsized constants in verilog frontend

This commit is contained in:
Clifford Wolf 2014-01-24 15:05:24 +01:00
parent 88fbdd4916
commit 0b47d907d3
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/verilog/const2ast.cc
View File

@ -99,7 +99,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
int bits_per_digit = my_ilog2(base-1);
if (len_in_bits < 0)
len_in_bits = digits.size() * bits_per_digit;
len_in_bits = std::max<int>(digits.size() * bits_per_digit, 32);
data.clear();
data.resize(len_in_bits);
@ -157,7 +157,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
if (*endptr == 0)
return AstNode::mkconst_int(intval, true);
// variable length constant
// unsized constant
if (str == endptr)
intval = -1;