mirror of https://github.com/YosysHQ/yosys.git
Fix extremely stupid typo
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@ -774,7 +774,7 @@ struct VerificImporter
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SigBit outsig = net_map.at(out);
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log_assert(outsig.wire && GetSize(outsig.wire) == 1);
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outsig.wire->attributes["\\init"] == Const(0, 1);
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outsig.wire->attributes["\\init"] = Const(0, 1);
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module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
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continue;
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