mirror of https://github.com/YosysHQ/yosys.git
Removed left over debug code
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@ -917,7 +917,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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children[0]->children[1]->clone() : children[0]->children[0]->clone());
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fake_ast->children[0]->delete_children();
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RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
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log_dump(width, shift_val, id2ast->range_swapped, source_width, id2ast->range_left, id2ast->range_right);
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if (id2ast->range_right != 0)
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shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right);
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if (id2ast->range_swapped)
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@ -1535,7 +1535,6 @@ skip_dynamic_range_lvalue_expansion:;
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tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1;
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tmp_range_right = (param_width + 2*param_offset) - children[0]->range_left - 1;
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}
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log_dump(param_upto, param_offset, param_width, children[0]->range_left, children[0]->range_right, tmp_range_left, tmp_range_right);
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for (int i = tmp_range_right; i <= tmp_range_left; i++) {
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int index = i - param_offset;
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if (0 <= index && index < param_width)
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