mirror of https://github.com/YosysHQ/yosys.git
Remove all PSL support code from verific.cc
This commit is contained in:
Clifford Wolf
parent
309f8fe74f
commit
0a31a0b3ae
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@ -104,9 +104,9 @@ void svapp_assume(VerificImporter *importer, Instance *inst);
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void svapp_cover(VerificImporter *importer, Instance *inst);
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struct VerificClockEdge {
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Net *clock_net;
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SigBit clock_sig;
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bool posedge;
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Net *clock_net = nullptr;
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SigBit clock_sig = State::Sx;
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bool posedge = false;
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VerificClockEdge(VerificImporter *importer, Instance *inst);
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};
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@ -121,7 +121,6 @@ struct VerificImporter
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bool mode_gates, mode_keep, mode_nosva, mode_nosvapp, mode_names, verbose;
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pool<int> verific_sva_prims;
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pool<int> verific_psl_prims;
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VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_nosvapp, bool mode_names, bool verbose) :
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mode_gates(mode_gates), mode_keep(mode_keep), mode_nosva(mode_nosva),
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@ -152,29 +151,6 @@ struct VerificImporter
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for (int p : sva_prims)
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verific_sva_prims.insert(p);
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// Copy&paste from Verific 3.16_484_32_170630 Netlist.h
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vector<int> psl_prims {
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OPER_PSLPREV, OPER_PSLNEXTFUNC, PRIM_PSL_ASSERT, PRIM_PSL_ASSUME,
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PRIM_PSL_ASSUME_GUARANTEE, PRIM_PSL_RESTRICT, PRIM_PSL_RESTRICT_GUARANTEE,
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PRIM_PSL_COVER, PRIM_ENDPOINT, PRIM_ROSE, PRIM_FELL, PRIM_AT, PRIM_ATSTRONG,
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PRIM_ABORT, PRIM_PSL_NOT, PRIM_PSL_AND, PRIM_PSL_OR, PRIM_IMPL, PRIM_EQUIV,
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PRIM_PSL_X, PRIM_PSL_XSTRONG, PRIM_PSL_G, PRIM_PSL_F, PRIM_PSL_U, PRIM_PSL_W,
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PRIM_NEXT, PRIM_NEXTSTRONG, PRIM_ALWAYS, PRIM_NEVER, PRIM_EVENTUALLY,
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PRIM_UNTIL, PRIM_UNTIL_, PRIM_UNTILSTRONG, PRIM_UNTILSTRONG_, PRIM_BEFORE,
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PRIM_BEFORE_, PRIM_BEFORESTRONG, PRIM_BEFORESTRONG_, PRIM_NEXT_A,
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PRIM_NEXT_ASTRONG, PRIM_NEXT_E, PRIM_NEXT_ESTRONG, PRIM_NEXT_EVENT,
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PRIM_NEXT_EVENTSTRONG, PRIM_NEXT_EVENT_A, PRIM_NEXT_EVENT_ASTRONG,
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PRIM_NEXT_EVENT_E, PRIM_NEXT_EVENT_ESTRONG, PRIM_SEQ_IMPL, PRIM_OSUFFIX_IMPL,
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PRIM_SUFFIX_IMPL, PRIM_OSUFFIX_IMPLSTRONG, PRIM_SUFFIX_IMPLSTRONG, PRIM_WITHIN,
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PRIM_WITHIN_, PRIM_WITHINSTRONG, PRIM_WITHINSTRONG_, PRIM_WHILENOT,
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PRIM_WHILENOT_, PRIM_WHILENOTSTRONG, PRIM_WHILENOTSTRONG_, PRIM_CONCAT,
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PRIM_FUSION, PRIM_SEQ_AND_LEN, PRIM_SEQ_AND, PRIM_SEQ_OR, PRIM_CONS_REP,
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PRIM_NONCONS_REP, PRIM_GOTO_REP
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};
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for (int p : psl_prims)
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verific_psl_prims.insert(p);
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}
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RTLIL::SigBit net_map_at(Net *net)
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@ -1126,20 +1102,20 @@ struct VerificImporter
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if (!mode_gates) {
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if (import_netlist_instance_cells(inst, inst_name))
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continue;
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if (inst->IsOperator() && !verific_sva_prims.count(inst->Type()) && !verific_psl_prims.count(inst->Type()))
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if (inst->IsOperator() && !verific_sva_prims.count(inst->Type()))
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log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name());
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} else {
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if (import_netlist_instance_gates(inst, inst_name))
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continue;
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}
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if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_PSL_ASSERT)
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if (inst->Type() == PRIM_SVA_ASSERT)
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sva_asserts.insert(inst);
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if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_PSL_ASSUME)
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if (inst->Type() == PRIM_SVA_ASSUME)
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sva_assumes.insert(inst);
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if (inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_PSL_COVER)
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if (inst->Type() == PRIM_SVA_COVER)
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sva_covers.insert(inst);
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if (inst->Type() == PRIM_SVA_PAST && !mode_nosva)
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@ -1159,38 +1135,9 @@ struct VerificImporter
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continue;
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}
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if (inst->Type() == OPER_PSLPREV && !mode_nosva)
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{
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Net *clock = inst->GetClock();
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if (!clock->IsConstant())
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{
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VerificClockEdge clock_edge(this, clock->Driver());
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SigSpec sig_d, sig_q;
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for (int i = 0; i < int(inst->InputSize()); i++) {
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sig_d.append(net_map_at(inst->GetInputBit(i)));
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sig_q.append(net_map_at(inst->GetOutputBit(i)));
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}
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if (verbose)
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig));
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RTLIL::Cell *ff = module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge);
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if (inst->InputSize() == 1)
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past_ffs.insert(ff);
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if (!mode_keep)
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continue;
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}
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}
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if (!mode_keep && (verific_sva_prims.count(inst->Type()) || verific_psl_prims.count(inst->Type()))) {
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if (!mode_keep && verific_sva_prims.count(inst->Type())) {
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if (verbose)
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log(" skipping SVA/PSL cell in non k-mode\n");
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log(" skipping SVA cell in non k-mode\n");
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continue;
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}
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@ -1202,7 +1149,7 @@ struct VerificImporter
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if (!mode_keep)
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log_error("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name());
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if (!verific_sva_prims.count(inst->Type()) && !verific_psl_prims.count(inst->Type()))
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if (!verific_sva_prims.count(inst->Type()))
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log_warning("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name());
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}
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@ -1277,36 +1224,6 @@ struct VerificImporter
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}
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};
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Net *verific_follow_inv(Net *w)
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{
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if (w == nullptr || w->IsMultipleDriven())
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return nullptr;
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Instance *i = w->Driver();
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if (i == nullptr || i->Type() != PRIM_INV)
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return nullptr;
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return i->GetInput();
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}
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Net *verific_follow_pslprev(Net *w)
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{
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if (w == nullptr || w->IsMultipleDriven())
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return nullptr;
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Instance *i = w->Driver();
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if (i == nullptr || i->Type() != OPER_PSLPREV || i->InputSize() != 1)
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return nullptr;
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return i->GetInputBit(0);
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}
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Net *verific_follow_inv_pslprev(Net *w)
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{
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w = verific_follow_inv(w);
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return verific_follow_pslprev(w);
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}
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VerificClockEdge::VerificClockEdge(VerificImporter *importer, Instance *inst)
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{
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log_assert(importer != nullptr);
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@ -1327,43 +1244,6 @@ VerificClockEdge::VerificClockEdge(VerificImporter *importer, Instance *inst)
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clock_sig = importer->net_map_at(clock_net);
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return;
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}
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// VHDL-flavored PSL clock
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if (inst->Type() == PRIM_AND)
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{
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Net *w1 = inst->GetInput1();
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Net *w2 = inst->GetInput2();
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clock_net = verific_follow_inv_pslprev(w1);
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if (clock_net == w2) {
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clock_sig = importer->net_map_at(clock_net);
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posedge = true;
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return;
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}
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clock_net = verific_follow_inv_pslprev(w2);
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if (clock_net == w1) {
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clock_sig = importer->net_map_at(clock_net);
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posedge = true;
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return;
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}
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clock_net = verific_follow_pslprev(w1);
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if (clock_net == verific_follow_inv(w2)) {
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clock_sig = importer->net_map_at(clock_net);
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posedge = false;
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return;
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}
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clock_net = verific_follow_pslprev(w2);
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if (clock_net == verific_follow_inv(w1)) {
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clock_sig = importer->net_map_at(clock_net);
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posedge = false;
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return;
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}
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log_abort();
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}
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}
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// ==================================================================
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@ -1393,8 +1273,7 @@ struct VerificSvaPP
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if (inst == nullptr)
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return nullptr;
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if (!importer->verific_sva_prims.count(inst->Type()) &&
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!importer->verific_psl_prims.count(inst->Type()))
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if (!importer->verific_sva_prims.count(inst->Type()))
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return nullptr;
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if (inst->Type() == PRIM_SVA_PAST)
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@ -1515,8 +1394,7 @@ struct VerificSvaImporter
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if (inst == nullptr)
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return nullptr;
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if (!importer->verific_sva_prims.count(inst->Type()) &&
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!importer->verific_psl_prims.count(inst->Type()))
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if (!importer->verific_sva_prims.count(inst->Type()))
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return nullptr;
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if (inst->Type() == PRIM_SVA_PAST)
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@ -1625,31 +1503,6 @@ struct VerificSvaImporter
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return;
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}
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// PSL Primitives
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if (inst->Type() == PRIM_ALWAYS)
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{
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parse_sequence(seq, inst->GetInput());
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return;
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}
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if (inst->Type() == PRIM_IMPL)
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{
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parse_sequence(seq, inst->GetInput1());
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seq.sig_en = module->And(NEW_ID, seq.sig_en, seq.sig_a);
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parse_sequence(seq, inst->GetInput2());
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return;
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}
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if (inst->Type() == PRIM_SUFFIX_IMPL)
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{
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parse_sequence(seq, inst->GetInput1());
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seq.sig_en = module->And(NEW_ID, seq.sig_en, seq.sig_a);
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sequence_ff(seq);
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parse_sequence(seq, inst->GetInput2());
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return;
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}
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// Handle unsupported primitives
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if (!importer->mode_keep)
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@ -1665,15 +1518,15 @@ struct VerificSvaImporter
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// parse SVA property clock event
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Instance *at_node = get_ast_input(root);
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log_assert(at_node && (at_node->Type() == PRIM_SVA_AT || at_node->Type() == PRIM_AT));
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log_assert(at_node && at_node->Type() == PRIM_SVA_AT);
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VerificClockEdge clock_edge(importer, at_node->Type() == PRIM_SVA_AT ? get_ast_input1(at_node) : at_node->GetInput2()->Driver());
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VerificClockEdge clock_edge(importer, get_ast_input1(at_node));
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clock = clock_edge.clock_sig;
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clock_posedge = clock_edge.posedge;
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// parse disable_iff expression
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Net *sequence_net = at_node->Type() == PRIM_SVA_AT ? at_node->GetInput2() : at_node->GetInput1();
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Net *sequence_net = at_node->GetInput2();
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while (1)
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{
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@ -1691,12 +1544,6 @@ struct VerificSvaImporter
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continue;
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}
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if (sequence_node && sequence_node->Type() == PRIM_ABORT) {
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disable_iff = importer->net_map_at(sequence_node->GetInput2());
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sequence_net = sequence_node->GetInput1();
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continue;
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}
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break;
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}
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@ -1846,7 +1693,7 @@ struct VerificPass : public Pass {
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log("Load the specified Verilog/SystemVerilog files into Verific.\n");
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log("\n");
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log("\n");
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log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl|-vhdpsl} <vhdl-file>..\n");
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log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
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log("\n");
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log("Load the specified VHDL files into Verific.\n");
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log("\n");
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@ -1900,8 +1747,7 @@ struct VerificPass : public Pass {
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log(" the checker logic inferred by it.\n");
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log("\n");
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log(" -nosva\n");
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log(" Ignore SVA properties, do not infer checker logic. (This also disables\n");
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log(" PSL properties in -vhdpsl mode.)\n");
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log(" Ignore SVA properties, do not infer checker logic.\n");
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log("\n");
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log(" -nosvapp\n");
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log(" Disable SVA properties pre-processing pass. This implies -nosva.\n");
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@ -2036,14 +1882,6 @@ struct VerificPass : public Pass {
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goto check_error;
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}
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if (GetSize(args) > argidx && args[argidx] == "-vhdpsl") {
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vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
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for (argidx++; argidx < GetSize(args); argidx++)
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if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_PSL))
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log_cmd_error("Reading `%s' in VHDL_PSL mode failed.\n", args[argidx].c_str());
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goto check_error;
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}
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if (GetSize(args) > argidx && args[argidx] == "-import")
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{
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std::set<Netlist*> nl_todo, nl_done;
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