mirror of https://github.com/YosysHQ/yosys.git
Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -569,6 +569,19 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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return true;
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}
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if (inst->Type() == OPER_SELECTOR)
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{
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module->addPmux(inst_name, State::S0, IN2, IN1, net_map_at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == OPER_WIDE_SELECTOR)
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{
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SigSpec out = OUT;
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module->addPmux(inst_name, SigSpec(State::S0, GetSize(out)), IN2, IN1, out);
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return true;
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}
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if (inst->Type() == OPER_WIDE_TRI) {
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module->addMux(inst_name, RTLIL::SigSpec(RTLIL::State::Sz, inst->OutputSize()), IN, net_map_at(inst->GetControl()), OUT);
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return true;
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