Added wire->upto flag for signals such as "wire [0:7] x;"

backends/ilang/ilang_backend.cc

@@ -123,6 +123,8 @@ void ILANG_BACKEND::dump_wire(FILE *f, std::string indent, const RTLIL::Wire *wi
 	fprintf(f, "%s" "wire ", indent.c_str());
 	if (wire->width != 1)
 		fprintf(f, "width %d ", wire->width);
+	if (wire->upto)
+		fprintf(f, "upto ");
 	if (wire->start_offset != 0)
 		fprintf(f, "offset %d ", wire->start_offset);
 	if (wire->port_input && !wire->port_output)

frontends/ast/genrtlil.cc

@@ -786,10 +786,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				log_error("Signal `%s' with non-constant width at %s:%d!\n",
 						str.c_str(), filename.c_str(), linenum);
 
+			bool wire_upto = false;
 			if (range_left < range_right && (range_left != -1 || range_right != 0)) {
 				int tmp = range_left;
 				range_left = range_right;
 				range_right = tmp;
+				wire_upto = true;
 			}
 
 			RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
@@ -798,6 +800,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			wire->port_id = port_id;
 			wire->port_input = is_input;
 			wire->port_output = is_output;
+			wire->upto = wire_upto;
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)

frontends/ilang/lexer.l

@@ -51,6 +51,7 @@
 "wire"		{ return TOK_WIRE; }
 "memory"	{ return TOK_MEMORY; }
 "width"		{ return TOK_WIDTH; }
+"upto"		{ return TOK_UPTO; }
 "offset"	{ return TOK_OFFSET; }
 "size"		{ return TOK_SIZE; }
 "input"		{ return TOK_INPUT; }

frontends/ilang/parser.y

@@ -54,7 +54,7 @@ using namespace ILANG_FRONTEND;
 %token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC
 %token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_INIT
 %token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET
-%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED
+%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED TOK_UPTO
 
 %type <sigspec> sigspec sigspec_list
 %type <integer> sync_type
@@ -135,6 +135,9 @@ wire_options:
 	wire_options TOK_WIDTH TOK_INT {
 		current_wire->width = $3;
 	} |
+	wire_options TOK_UPTO {
+		current_wire->upto = true;
+	} |
 	wire_options TOK_OFFSET TOK_INT {
 		current_wire->start_offset = $3;
 	} |

kernel/rtlil.cc

@@ -1019,6 +1019,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
 	wire->port_id = other->port_id;
 	wire->port_input = other->port_input;
 	wire->port_output = other->port_output;
+	wire->upto = other->upto;
 	wire->attributes = other->attributes;
 	return wire;
 }
@@ -1443,6 +1444,7 @@ RTLIL::Wire::Wire()
 	port_id = 0;
 	port_input = false;
 	port_output = false;
+	upto = false;
 }
 
 RTLIL::Memory::Memory()

kernel/rtlil.h

@@ -602,7 +602,7 @@ public:
 
 	RTLIL::IdString name;
 	int width, start_offset, port_id;
-	bool port_input, port_output;
+	bool port_input, port_output, upto;
 	RTLIL_ATTRIBUTE_MEMBERS
 };