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Improved ast dumping (ast/verilog frontend)

This commit is contained in:
Clifford Wolf 2013-08-19 19:49:14 +02:00
parent a860efa8ac
commit 4214561890
4 changed files with 35 additions and 64 deletions
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68
frontends/ast/ast.cc
View File

@ -46,7 +46,7 @@ namespace AST {
// instanciate global variables (private API)
namespace AST_INTERNAL {
bool flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
AstNode *current_ast, *current_ast_mod;
std::map<std::string, AstNode*> current_scope;
RTLIL::SigSpec *genRTLIL_subst_from = NULL;
@ -212,47 +212,13 @@ AstNode::~AstNode()
// create a nice text representation of the node
// (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
void AstNode::dumpAst(FILE *f, std::string indent, AstNode *other)
void AstNode::dumpAst(FILE *f, std::string indent)
{
if (f == NULL) {
for (auto f : log_files)
dumpAst(f, indent, other);
dumpAst(f, indent);
return;
}
if (other != NULL) {
if (type != other->type)
goto found_diff_to_other;
if (children.size() != other->children.size())
goto found_diff_to_other;
if (str != other->str)
goto found_diff_to_other;
if (bits != other->bits)
goto found_diff_to_other;
if (is_input != other->is_input)
goto found_diff_to_other;
if (is_output != other->is_output)
goto found_diff_to_other;
if (is_reg != other->is_reg)
goto found_diff_to_other;
if (is_signed != other->is_signed)
goto found_diff_to_other;
if (range_valid != other->range_valid)
goto found_diff_to_other;
if (port_id != other->port_id)
goto found_diff_to_other;
if (range_left != other->range_left)
goto found_diff_to_other;
if (range_right != other->range_right)
goto found_diff_to_other;
if (integer != other->integer)
goto found_diff_to_other;
if (0) {
found_diff_to_other:
other->dumpAst(f, indent + "- ");
this->dumpAst(f, indent + "+ ");
return;
}
}
std::string type_name = type2str(type);
fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
@ -284,7 +250,7 @@ void AstNode::dumpAst(FILE *f, std::string indent, AstNode *other)
fprintf(f, "\n");
for (size_t i = 0; i < children.size(); i++)
children[i]->dumpAst(f, indent + " ", other ? other->children[i] : NULL);
children[i]->dumpAst(f, indent + " ");
}
// helper function for AstNode::dumpVlog()
@ -675,11 +641,17 @@ static AstModule* process_module(AstNode *ast)
current_ast_mod = ast;
AstNode *ast_before_simplify = ast->clone();
if (flag_dump_ast1) {
log("Dumping verilog AST before simplification:\n");
ast->dumpAst(NULL, " ");
log("--- END OF AST DUMP ---\n");
}
while (ast->simplify(!flag_noopt, false, false, 0)) { }
if (flag_dump_ast) {
log("Dumping verilog AST (as requested by %s option):\n", flag_dump_ast_diff ? "dump_ast_diff" : "dump_ast");
ast->dumpAst(NULL, " ", flag_dump_ast_diff ? ast_before_simplify : NULL);
if (flag_dump_ast2) {
log("Dumping verilog AST after simplification:\n");
ast->dumpAst(NULL, " ");
log("--- END OF AST DUMP ---\n");
}
@ -746,11 +718,11 @@ static AstModule* process_module(AstNode *ast)
}
// create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast, bool dump_ast_diff, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt)
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt)
{
current_ast = ast;
flag_dump_ast = dump_ast;
flag_dump_ast_diff = dump_ast_diff;
flag_dump_ast1 = dump_ast1;
flag_dump_ast2 = dump_ast2;
flag_dump_vlog = dump_vlog;
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;
@ -780,8 +752,8 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", name.c_str());
current_ast = NULL;
flag_dump_ast = false;
flag_dump_ast_diff = false;
flag_dump_ast1 = false;
flag_dump_ast2 = false;
flag_dump_vlog = false;
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;
@ -865,8 +837,8 @@ void AstModule::update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes)
log_header("Executing AST frontend in update_auto_wires mode using pre-parsed AST for module `%s'.\n", name.c_str());
current_ast = NULL;
flag_dump_ast = false;
flag_dump_ast_diff = false;
flag_dump_ast1 = false;
flag_dump_ast2 = false;
flag_dump_vlog = false;
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;

6
frontends/ast/ast.h
View File

@ -171,7 +171,7 @@ namespace AST
void meminfo(int &mem_width, int &mem_size, int &addr_bits);
// create a human-readable text representation of the AST (for debugging)
void dumpAst(FILE *f, std::string indent, AstNode *other = NULL);
void dumpAst(FILE *f, std::string indent);
void dumpVlog(FILE *f, std::string indent);
// used by genRTLIL() for detecting expression width and sign
@ -195,7 +195,7 @@ namespace AST
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast = false, bool dump_ast_diff = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false);
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false);
// parametric modules are supported directly by the AST library
// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
@ -224,7 +224,7 @@ namespace AST
namespace AST_INTERNAL
{
// internal state variables
extern bool flag_dump_ast, flag_dump_ast_diff, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
extern AST::AstNode *current_ast, *current_ast_mod;
extern std::map<std::string, AST::AstNode*> current_scope;
extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial;

2
frontends/ast/simplify.cc
View File

@ -243,7 +243,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
// resolve constant prefixes
if (type == AST_PREFIX) {
if (children[0]->type != AST_CONSTANT) {
dumpAst(NULL, "> ", NULL);
dumpAst(NULL, "> ");
log_error("Index in generate block prefix syntax at %s:%d is not constant!\n", filename.c_str(), linenum);
}
assert(children[1]->type == AST_IDENTIFIER);

23
frontends/verilog/verilog_frontend.cc
View File

@ -49,11 +49,11 @@ struct VerilogFrontend : public Frontend {
log("Load modules from a verilog file to the current design. A large subset of\n");
log("Verilog-2005 is supported.\n");
log("\n");
log(" -dump_ast\n");
log(" dump abstract syntax tree (after simplification)\n");
log(" -dump_ast1\n");
log(" dump abstract syntax tree (before simplification)\n");
log("\n");
log(" -dump_ast_diff\n");
log(" dump ast differences before and after simplification\n");
log(" -dump_ast2\n");
log(" dump abstract syntax tree (after simplification)\n");
log("\n");
log(" -dump_vlog\n");
log(" dump ast as verilog code (after simplification)\n");
@ -103,8 +103,8 @@ struct VerilogFrontend : public Frontend {
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
bool flag_dump_ast = false;
bool flag_dump_ast_diff = false;
bool flag_dump_ast1 = false;
bool flag_dump_ast2 = false;
bool flag_dump_vlog = false;
bool flag_nolatches = false;
bool flag_nomem2reg = false;
@ -121,13 +121,12 @@ struct VerilogFrontend : public Frontend {
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-dump_ast") {
flag_dump_ast = true;
if (arg == "-dump_ast1") {
flag_dump_ast1 = true;
continue;
}
if (arg == "-dump_ast_diff") {
flag_dump_ast = true;
flag_dump_ast_diff = true;
if (arg == "-dump_ast2") {
flag_dump_ast2 = true;
continue;
}
if (arg == "-dump_vlog") {
@ -205,7 +204,7 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yyparse();
frontend_verilog_yylex_destroy();
AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt);
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt);
if (!flag_nopp)
fclose(fp);