riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed O(n^2) performance bug in verilog preprocessor

This commit is contained in:
Clifford Wolf 2013-11-22 14:08:43 +01:00
parent 058ceda6a0
commit a362fd81ae
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
frontends/verilog/preproc.cc
View File

@ -62,7 +62,7 @@ static void insert_input(std::string str)
static char next_char()
{
if (input_buffer.size() == 0)
if (input_buffer.empty())
return 0;
assert(input_buffer_charp <= input_buffer.front().size());