mirror of https://github.com/YosysHQ/yosys.git
Added found_real feature to AstNode::detectSignWidth
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@ -214,8 +214,8 @@ namespace AST
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void dumpVlog(FILE *f, std::string indent);
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// used by genRTLIL() for detecting expression width and sign
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void detectSignWidthWorker(int &width_hint, bool &sign_hint);
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void detectSignWidth(int &width_hint, bool &sign_hint);
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void detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);
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void detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);
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// create RTLIL code for this AST node
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// for expressions the resulting signal vector is returned
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@ -585,7 +585,7 @@ struct AST_INTERNAL::ProcessGenerator
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};
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// detect sign and width of an expression
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void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
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void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
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{
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std::string type_name;
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bool sub_sign_hint = true;
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@ -603,6 +603,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
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break;
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case AST_REALVALUE:
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if (found_real)
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*found_real = true;
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width_hint = std::max(width_hint, 32);
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break;
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@ -788,10 +790,13 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
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}
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// detect sign and width of an expression
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void AstNode::detectSignWidth(int &width_hint, bool &sign_hint)
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void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real)
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{
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width_hint = -1, sign_hint = true;
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detectSignWidthWorker(width_hint, sign_hint);
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width_hint = -1;
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sign_hint = true;
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if (found_real)
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*found_real = false;
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detectSignWidthWorker(width_hint, sign_hint, found_real);
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}
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// create RTLIL from an AST node
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