mirror of https://github.com/YosysHQ/yosys.git
bugfix in blif front-end
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@ -207,10 +207,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name)
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RTLIL::SigSpec input_sig, output_sig;
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while ((p = strtok(NULL, " \t\r\n")) != NULL) {
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RTLIL::Wire *wire;
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if (module->wires_.count(stringf("\\%s", p)) > 0) {
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wire = module->wires_.at(stringf("\\%s", p));
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if (module->wires_.count(RTLIL::escape_id(p)) > 0) {
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wire = module->wires_.at(RTLIL::escape_id(p));
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} else {
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wire = module->addWire(stringf("\\%s", p));
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wire = module->addWire(RTLIL::escape_id(p));
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}
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input_sig.append(wire);
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}
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@ -6,8 +6,8 @@ source common.sh
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f=$1
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n=$(basename ${f%.v})
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test_febe vlog1 "synth" ".v" "write_verilog" "read_verilog" "-ignore_div_by_zero" $n $f
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test_febe vlog2 "synth -run coarse" ".v" "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f
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test_febe blif "synth; splitnets -ports" ".blif" "write_blif -icells" "read_blif" "-ignore_div_by_zero" $n $f
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test_febe vlog1 "synth" ".v" "write_verilog" "read_verilog" "-ignore_div_by_zero" $n $f
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test_febe vlog2 "synth -run coarse" ".v" "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f
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test_febe blif "synth; splitnets -ports" ".blif" "write_blif" "read_blif" "-ignore_div_by_zero" $n $f
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exit 0
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