riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)

This commit is contained in:
Clifford Wolf 2013-03-31 11:19:11 +02:00
parent 5640b7d607
commit 161565be10
5 changed files with 15 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
frontends/ast/ast.cc
View File

@ -122,6 +122,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_CELL)
X(AST_PRIMITIVE)
X(AST_ALWAYS)
X(AST_INITIAL)
X(AST_BLOCK)
X(AST_ASSIGN_EQ)
X(AST_ASSIGN_LE)
@ -417,6 +418,14 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
}
break;
case AST_INITIAL:
fprintf(f, "%s" "initial\n", indent.c_str());
for (auto child : children) {
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
child->dumpVlog(f, indent + " ");
}
break;
case AST_POSEDGE:
case AST_NEGEDGE:
case AST_EDGE:

1
frontends/ast/ast.h
View File

@ -103,6 +103,7 @@ namespace AST
AST_CELL,
AST_PRIMITIVE,
AST_ALWAYS,
AST_INITIAL,
AST_BLOCK,
AST_ASSIGN_EQ,
AST_ASSIGN_LE,

4
frontends/ast/genrtlil.cc
View File

@ -310,6 +310,7 @@ struct AST_INTERNAL::ProcessGenerator
case AST_COND:
case AST_ALWAYS:
case AST_INITIAL:
for (auto child : ast->children)
if (child->type == AST_BLOCK)
collect_lvalues(reg, child, type_eq, type_le, false);
@ -1013,7 +1014,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
break;
// use ProcessGenerator for always blocks
case AST_ALWAYS: {
case AST_ALWAYS:
case AST_INITIAL: {
AstNode *always = this->clone();
ProcessGenerator generator(always);
delete always;

2
frontends/ast/simplify.cc
View File

@ -196,7 +196,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
current_block = this;
current_block_child = children[i];
}
if (type == AST_ALWAYS && children[i]->type == AST_BLOCK)
if ((type == AST_ALWAYS || type == AST_INITIAL) && children[i]->type == AST_BLOCK)
current_top_block = children[i];
did_something_here = children[i]->simplify(const_fold_here, at_zero, in_lvalue_here, stage);
if (did_something_here)

2
frontends/verilog/parser.y
View File

@ -607,7 +607,7 @@ always_stmt:
ast_stack.pop_back();
} |
attr TOK_INITIAL {
AstNode *node = new AstNode(AST_ALWAYS);
AstNode *node = new AstNode(AST_INITIAL);
append_attr(node, $1);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);