mirror of https://github.com/YosysHQ/yosys.git
Added Verilog parser support for asserts
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@ -80,6 +80,7 @@ std::string AST::type2str(AstNodeType type)
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X(AST_CELLTYPE)
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X(AST_IDENTIFIER)
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X(AST_PREFIX)
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X(AST_ASSERT)
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X(AST_FCALL)
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X(AST_TO_SIGNED)
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X(AST_TO_UNSIGNED)
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@ -58,6 +58,7 @@ namespace AST
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AST_CELLTYPE,
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AST_IDENTIFIER,
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AST_PREFIX,
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AST_ASSERT,
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AST_FCALL,
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AST_TO_SIGNED,
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@ -113,6 +113,8 @@ namespace VERILOG_FRONTEND {
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"generate" { return TOK_GENERATE; }
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"endgenerate" { return TOK_ENDGENERATE; }
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"assert"([ \t\r\n]+"property")? { return TOK_ASSERT; }
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"input" { return TOK_INPUT; }
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"output" { return TOK_OUTPUT; }
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"inout" { return TOK_INOUT; }
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@ -104,7 +104,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
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%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR
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%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
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%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
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%token TOK_POS_INDEXED TOK_NEG_INDEXED
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%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT
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%type <ast> wire_type range non_opt_range expr basic_expr concat_list rvalue lvalue lvalue_concat_list
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%type <string> opt_label tok_prim_wrapper hierarchical_id
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@ -366,7 +366,7 @@ module_body:
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module_body_stmt:
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task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt |
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always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr;
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always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert;
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task_func_decl:
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TOK_TASK TOK_ID ';' {
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@ -748,6 +748,11 @@ opt_label:
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$$ = NULL;
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};
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assert:
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TOK_ASSERT '(' expr ')' ';' {
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ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $3));
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};
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simple_behavioral_stmt:
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lvalue '=' expr {
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AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $3);
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@ -760,7 +765,7 @@ simple_behavioral_stmt:
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// this production creates the obligatory if-else shift/reduce conflict
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behavioral_stmt:
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defattr | wire_decl |
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defattr | assert | wire_decl |
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simple_behavioral_stmt ';' |
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hierarchical_id attr {
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AstNode *node = new AstNode(AST_TCALL);
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