mirror of https://github.com/YosysHQ/yosys.git
Fixed RTLIL code generator for part select of parameter
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0598bc8708
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55521c085a
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@ -912,7 +912,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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children[0]->children[1]->clone() : children[0]->children[0]->clone());
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fake_ast->children[0]->delete_children();
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RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width,
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fake_ast->children[0]->genRTLIL(), !wire->upto ? fake_ast->children[1]->genRTLIL() :
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fake_ast->children[0]->genRTLIL(), !id2ast->range_swapped ? fake_ast->children[1]->genRTLIL() :
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current_module->Sub(NEW_ID, RTLIL::SigSpec(wire->width - width), fake_ast->children[1]->genRTLIL()));
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delete left_at_zero_ast;
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delete right_at_zero_ast;
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@ -924,7 +924,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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str.c_str(), filename.c_str(), linenum);
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chunk.width = children[0]->range_left - children[0]->range_right + 1;
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chunk.offset = children[0]->range_right - id2ast->range_right;
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if (wire->upto)
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if (id2ast->range_swapped)
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chunk.offset = wire->width - (chunk.offset + chunk.width);
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}
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}
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