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Fixed RTLIL code generator for part select of parameter

This commit is contained in:
Clifford Wolf 2014-07-28 15:31:19 +02:00
parent 0598bc8708
commit 55521c085a
1 changed files with 2 additions and 2 deletions
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4
frontends/ast/genrtlil.cc
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@ -912,7 +912,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
children[0]->children[1]->clone() : children[0]->children[0]->clone());
fake_ast->children[0]->delete_children();
RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width,
fake_ast->children[0]->genRTLIL(), !wire->upto ? fake_ast->children[1]->genRTLIL() :
fake_ast->children[0]->genRTLIL(), !id2ast->range_swapped ? fake_ast->children[1]->genRTLIL() :
current_module->Sub(NEW_ID, RTLIL::SigSpec(wire->width - width), fake_ast->children[1]->genRTLIL()));
delete left_at_zero_ast;
delete right_at_zero_ast;
@ -924,7 +924,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
str.c_str(), filename.c_str(), linenum);
chunk.width = children[0]->range_left - children[0]->range_right + 1;
chunk.offset = children[0]->range_right - id2ast->range_right;
if (wire->upto)
if (id2ast->range_swapped)
chunk.offset = wire->width - (chunk.offset + chunk.width);
}
}