mirror of https://github.com/YosysHQ/yosys.git
Added ff and latch support to read_liberty
This commit is contained in:
Clifford Wolf
parent
96b1ebc8dc
commit
118517ca5a
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@ -160,7 +160,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
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}
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if (0 <= top && stack[top].type == 2) {
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if (next_token.type == '*' || next_token.type == '&' || next_token.type == 0)
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if (next_token.type == '*' || next_token.type == '&' || next_token.type == 0 || next_token.type == '(')
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return false;
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stack[top].type = 3;
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return true;
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@ -225,6 +225,223 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
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return stack.back().sig;
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}
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static void create_ff(RTLIL::Module *module, LibertyAst *node)
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{
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RTLIL::SigSpec iq_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(1))));
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RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig;
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bool clk_polarity = true, clear_polarity = true, preset_polarity = true;
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for (auto child : node->children) {
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if (child->id == "clocked_on")
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clk_sig = parse_func_expr(module, child->value.c_str());
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if (child->id == "next_state")
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data_sig = parse_func_expr(module, child->value.c_str());
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if (child->id == "clear")
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clear_sig = parse_func_expr(module, child->value.c_str());
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if (child->id == "preset")
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preset_sig = parse_func_expr(module, child->value.c_str());
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}
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if (clk_sig.width == 0 || data_sig.width == 0)
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log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", RTLIL::id2cstr(module->name));
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for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
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{
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rerun_invert_rollback = false;
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for (auto &it : module->cells) {
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if (it.second->type == "$_INV_" && it.second->connections.at("\\Y") == clk_sig) {
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clk_sig = it.second->connections.at("\\A");
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clk_polarity = !clk_polarity;
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rerun_invert_rollback = true;
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}
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if (it.second->type == "$_INV_" && it.second->connections.at("\\Y") == clear_sig) {
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clear_sig = it.second->connections.at("\\A");
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clear_polarity = !clear_polarity;
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rerun_invert_rollback = true;
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}
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if (it.second->type == "$_INV_" && it.second->connections.at("\\Y") == preset_sig) {
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preset_sig = it.second->connections.at("\\A");
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preset_polarity = !preset_polarity;
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rerun_invert_rollback = true;
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}
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}
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}
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$_INV_";
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cell->connections["\\A"] = iq_sig;
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cell->connections["\\Y"] = iqn_sig;
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module->add(cell);
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cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->connections["\\D"] = data_sig;
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cell->connections["\\Q"] = iq_sig;
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cell->connections["\\C"] = clk_sig;
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module->add(cell);
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if (clear_sig.width == 0 && preset_sig.width == 0) {
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cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
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}
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if (clear_sig.width == 1 && preset_sig.width == 0) {
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cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
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cell->connections["\\R"] = clear_sig;
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}
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if (clear_sig.width == 0 && preset_sig.width == 1) {
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cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
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cell->connections["\\R"] = preset_sig;
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}
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if (clear_sig.width == 1 && preset_sig.width == 1) {
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cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
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cell->connections["\\S"] = preset_sig;
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cell->connections["\\R"] = clear_sig;
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}
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log_assert(!cell->type.empty());
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}
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static void create_latch(RTLIL::Module *module, LibertyAst *node)
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{
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RTLIL::SigSpec iq_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(1))));
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RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig;
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bool enable_polarity = true, clear_polarity = true, preset_polarity = true;
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for (auto child : node->children) {
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if (child->id == "enable")
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enable_sig = parse_func_expr(module, child->value.c_str());
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if (child->id == "data_in")
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data_sig = parse_func_expr(module, child->value.c_str());
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if (child->id == "clear")
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clear_sig = parse_func_expr(module, child->value.c_str());
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if (child->id == "preset")
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preset_sig = parse_func_expr(module, child->value.c_str());
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}
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if (enable_sig.width == 0 || data_sig.width == 0)
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log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::id2cstr(module->name));
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for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
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{
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rerun_invert_rollback = false;
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for (auto &it : module->cells) {
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if (it.second->type == "$_INV_" && it.second->connections.at("\\Y") == enable_sig) {
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enable_sig = it.second->connections.at("\\A");
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enable_polarity = !enable_polarity;
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rerun_invert_rollback = true;
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}
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if (it.second->type == "$_INV_" && it.second->connections.at("\\Y") == clear_sig) {
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clear_sig = it.second->connections.at("\\A");
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clear_polarity = !clear_polarity;
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rerun_invert_rollback = true;
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}
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if (it.second->type == "$_INV_" && it.second->connections.at("\\Y") == preset_sig) {
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preset_sig = it.second->connections.at("\\A");
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preset_polarity = !preset_polarity;
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rerun_invert_rollback = true;
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}
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}
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}
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$_INV_";
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cell->connections["\\A"] = iq_sig;
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cell->connections["\\Y"] = iqn_sig;
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module->add(cell);
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if (clear_sig.width == 1)
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{
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RTLIL::SigSpec clear_negative = clear_sig;
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RTLIL::SigSpec clear_enable = clear_sig;
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if (clear_polarity == true || clear_polarity != enable_polarity)
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{
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RTLIL::Cell *inv = new RTLIL::Cell;
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inv->name = NEW_ID;
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inv->type = "$_INV_";
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inv->connections["\\A"] = clear_sig;
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inv->connections["\\Y"] = NEW_WIRE(module, 1);;
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module->add(inv);
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if (clear_polarity == true)
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clear_negative = inv->connections["\\Y"];
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if (clear_polarity != enable_polarity)
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clear_enable = inv->connections["\\Y"];
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}
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RTLIL::Cell *data_gate = new RTLIL::Cell;
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data_gate->name = NEW_ID;
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data_gate->type = "$_AND_";
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data_gate->connections["\\A"] = data_sig;
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data_gate->connections["\\B"] = clear_negative;
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data_gate->connections["\\Y"] = data_sig = NEW_WIRE(module, 1);;
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module->add(data_gate);
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RTLIL::Cell *enable_gate = new RTLIL::Cell;
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enable_gate->name = NEW_ID;
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enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_";
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enable_gate->connections["\\A"] = enable_sig;
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enable_gate->connections["\\B"] = clear_enable;
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enable_gate->connections["\\Y"] = data_sig = NEW_WIRE(module, 1);;
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module->add(enable_gate);
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}
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if (preset_sig.width == 1)
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{
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RTLIL::SigSpec preset_positive = preset_sig;
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RTLIL::SigSpec preset_enable = preset_sig;
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if (preset_polarity == false || preset_polarity != enable_polarity)
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{
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RTLIL::Cell *inv = new RTLIL::Cell;
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inv->name = NEW_ID;
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inv->type = "$_INV_";
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inv->connections["\\A"] = preset_sig;
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inv->connections["\\Y"] = NEW_WIRE(module, 1);;
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module->add(inv);
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if (preset_polarity == false)
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preset_positive = inv->connections["\\Y"];
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if (preset_polarity != enable_polarity)
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preset_enable = inv->connections["\\Y"];
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}
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RTLIL::Cell *data_gate = new RTLIL::Cell;
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data_gate->name = NEW_ID;
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data_gate->type = "$_OR_";
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data_gate->connections["\\A"] = data_sig;
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data_gate->connections["\\B"] = preset_positive;
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data_gate->connections["\\Y"] = data_sig = NEW_WIRE(module, 1);;
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module->add(data_gate);
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RTLIL::Cell *enable_gate = new RTLIL::Cell;
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enable_gate->name = NEW_ID;
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enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_";
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enable_gate->connections["\\A"] = enable_sig;
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enable_gate->connections["\\B"] = preset_enable;
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enable_gate->connections["\\Y"] = data_sig = NEW_WIRE(module, 1);;
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module->add(enable_gate);
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}
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cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N');
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cell->connections["\\D"] = data_sig;
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cell->connections["\\Q"] = iq_sig;
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cell->connections["\\E"] = enable_sig;
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module->add(cell);
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}
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struct LibertyFrontend : public Frontend {
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LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { }
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virtual void help()
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@ -289,21 +506,6 @@ struct LibertyFrontend : public Frontend {
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log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
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}
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if (!flag_lib)
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{
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LibertyAst *ff = cell->find("ff");
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if (ff != NULL) {
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log("Warning: skipping flip-flop cell %s.\n", RTLIL::id2cstr(cell_name));
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continue;
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}
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LibertyAst *latch = cell->find("latch");
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if (latch != NULL) {
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log("Warning: skipping latch cell %s.\n", RTLIL::id2cstr(cell_name));
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continue;
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}
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}
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// log("Processing cell type %s.\n", RTLIL::id2cstr(cell_name));
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cell_count++;
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@ -314,39 +516,51 @@ struct LibertyFrontend : public Frontend {
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for (auto &attr : attributes)
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module->attributes[attr] = 1;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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LibertyAst *dir = pin->find("direction");
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if (dir == NULL || dir->value == "internal")
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continue;
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log_assert(dir->value == "input" || dir->value == "output");
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = RTLIL::escape_id(pin->args.at(0));
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module->add(wire);
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if (dir->value == "input") {
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wire->port_input = true;
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continue;
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for (auto node : cell->children)
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if (node->id == "pin" && node->args.size() == 1) {
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LibertyAst *dir = node->find("direction");
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if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "internal"))
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log_error("Missing or invalid dircetion for pin %s of cell %s.\n", node->args.at(0).c_str(), RTLIL::id2cstr(module->name));
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if (!flag_lib || dir->value != "internal")
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module->new_wire(1, RTLIL::escape_id(node->args.at(0)));
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}
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wire->port_output = true;
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for (auto node : cell->children)
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{
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if (!flag_lib) {
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if (node->id == "ff" && node->args.size() == 2)
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create_ff(module, node);
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if (node->id == "latch" && node->args.size() == 2)
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create_latch(module, node);
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}
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if (flag_lib)
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continue;
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if (node->id == "pin" && node->args.size() == 1)
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{
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LibertyAst *dir = node->find("direction");
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LibertyAst *func = pin->find("function");
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if (func == NULL)
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log_error("Missing function on output %s of cell %s.\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name));
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if (flag_lib && dir->value == "internal")
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continue;
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RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
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module->connections.push_back(RTLIL::SigSig(wire, out_sig));
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RTLIL::Wire *wire = module->wires.at(RTLIL::escape_id(node->args.at(0)));
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continue;
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if (dir && dir->value == "input") {
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wire->port_input = true;
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continue;
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}
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if (dir && dir->value == "output")
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wire->port_output = true;
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if (flag_lib)
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continue;
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LibertyAst *func = node->find("function");
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if (func == NULL)
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log_error("Missing function on output %s of cell %s.\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name));
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RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
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module->connections.push_back(RTLIL::SigSig(wire, out_sig));
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}
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}
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module->fixup_ports();
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