mirror of https://github.com/YosysHQ/yosys.git
Fixed segfault on invalid verilog constant 1'b_
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@ -122,7 +122,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
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}
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int len = GetSize(data);
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RTLIL::State msb = data.back();
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RTLIL::State msb = data.empty() ? RTLIL::S0 : data.back();
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if (len_in_bits < 0) {
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if (len < 32)
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