mirror of https://github.com/YosysHQ/yosys.git
Added liberty frontend
This commit is contained in:
Clifford Wolf
parent
45d2b6ffce
commit
4440610d3f
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OBJS += frontends/liberty/liberty.o
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "passes/techmap/libparse.h"
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#include "kernel/register.h"
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#include "kernel/log.h"
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using namespace PASS_DFFLIBMAP;
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struct token_t {
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char type;
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RTLIL::SigSpec sig;
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token_t (char t) : type(t) { }
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token_t (char t, RTLIL::SigSpec s) : type(t), sig(s) { }
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};
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static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&expr)
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{
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log_assert(*expr != 0);
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int id_len = 0;
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while (('a' <= expr[id_len] && expr[id_len] <= 'z') || ('A' <= expr[id_len] && expr[id_len] <= 'Z') ||
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('0' <= expr[id_len] && expr[id_len] <= '9') || expr[id_len] == '.' || expr[id_len] == '_') id_len++;
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if (id_len == 0)
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log_error("Expected identifier at `%s'.\n", expr);
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if (id_len == 1 && (*expr == '0' || *expr == '1'))
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return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
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std::string id = RTLIL::escape_id(std::string(expr, id_len));
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if (!module->wires.count(id))
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log_error("Can't resolve wire name %s.\n", RTLIL::id2cstr(id));
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expr += id_len;
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return module->wires.at(id);
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}
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static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$_INV_";
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cell->connections["\\A"] = A;
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cell->connections["\\Y"] = NEW_WIRE(module, 1);
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module->add(cell);
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return cell->connections["\\Y"];
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}
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static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$_XOR_";
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cell->connections["\\A"] = A;
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cell->connections["\\B"] = B;
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cell->connections["\\Y"] = NEW_WIRE(module, 1);
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module->add(cell);
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return cell->connections["\\Y"];
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}
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static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$_AND_";
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cell->connections["\\A"] = A;
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cell->connections["\\B"] = B;
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cell->connections["\\Y"] = NEW_WIRE(module, 1);
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module->add(cell);
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return cell->connections["\\Y"];
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}
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static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$_OR_";
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cell->connections["\\A"] = A;
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cell->connections["\\B"] = B;
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cell->connections["\\Y"] = NEW_WIRE(module, 1);
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module->add(cell);
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return cell->connections["\\Y"];
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}
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static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
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{
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int top = int(stack.size())-1;
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if (0 <= top-1 && stack[top].type == 0 && stack[top-1].type == '!') {
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token_t t = token_t(0, create_inv_cell(module, stack[top].sig));
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stack.pop_back();
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stack.pop_back();
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stack.push_back(t);
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return true;
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}
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if (0 <= top-1 && stack[top].type == '\'' && stack[top-1].type == 0) {
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token_t t = token_t(0, create_inv_cell(module, stack[top-1].sig));
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stack.pop_back();
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stack.pop_back();
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stack.push_back(t);
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return true;
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}
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if (0 <= top && stack[top].type == 0) {
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if (next_token.type == '\'')
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return false;
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stack[top].type = 1;
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return true;
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}
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if (0 <= top-2 && stack[top-2].type == 1 && stack[top-1].type == '^' && stack[top].type == 1) {
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token_t t = token_t(1, create_xor_cell(module, stack[top-2].sig, stack[top].sig));
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stack.pop_back();
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stack.pop_back();
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stack.pop_back();
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stack.push_back(t);
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return true;
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}
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if (0 <= top && stack[top].type == 1) {
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if (next_token.type == '^')
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return false;
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stack[top].type = 2;
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return true;
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}
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if (0 <= top-1 && stack[top-1].type == 2 && stack[top].type == 2) {
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token_t t = token_t(2, create_and_cell(module, stack[top-2].sig, stack[top].sig));
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stack.pop_back();
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stack.pop_back();
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stack.pop_back();
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stack.push_back(t);
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return true;
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}
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if (0 <= top-2 && stack[top-2].type == 2 && (stack[top-1].type == '*' || stack[top-1].type == '&') && stack[top].type == 2) {
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token_t t = token_t(2, create_and_cell(module, stack[top-2].sig, stack[top].sig));
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stack.pop_back();
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stack.pop_back();
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stack.pop_back();
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stack.push_back(t);
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return true;
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}
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if (0 <= top && stack[top].type == 2) {
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if (next_token.type == '*' || next_token.type == '&' || next_token.type == 0)
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return false;
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stack[top].type = 3;
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return true;
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}
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if (0 <= top-2 && stack[top-2].type == 3 && (stack[top-1].type == '+' || stack[top-1].type == '|') && stack[top].type == 3) {
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token_t t = token_t(3, create_or_cell(module, stack[top-2].sig, stack[top].sig));
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stack.pop_back();
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stack.pop_back();
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stack.pop_back();
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stack.push_back(t);
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return true;
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}
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if (0 <= top-2 && stack[top-2].type == '(' && stack[top-1].type == 3 && stack[top].type == ')') {
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token_t t = token_t(0, stack[top-1].sig);
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stack.pop_back();
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stack.pop_back();
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stack.pop_back();
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stack.push_back(t);
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return true;
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}
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return false;
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}
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static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
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{
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const char *orig_expr = expr;
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std::vector<token_t> stack;
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while (*expr)
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{
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if (*expr == ' ' || *expr == '\t' || *expr == '\r' || *expr == '\n' || *expr == '"') {
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expr++;
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continue;
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}
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token_t next_token(0);
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if (*expr == '(' || *expr == ')' || *expr == '\'' || *expr == '!' || *expr == '^' || *expr == '*' || *expr == '+' || *expr == '|')
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next_token = token_t(*(expr++));
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else
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next_token = token_t(0, parse_func_identifier(module, expr));
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while (parse_func_reduce(module, stack, next_token)) {}
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stack.push_back(next_token);
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}
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while (parse_func_reduce(module, stack, token_t('.'))) {}
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#if 0
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for (size_t i = 0; i < stack.size(); i++)
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if (stack[i].type < 16)
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log("%3d: %d %s\n", int(i), stack[i].type, log_signal(stack[i].sig));
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else
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log("%3d: %c\n", int(i), stack[i].type);
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#endif
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if (stack.size() != 1 || stack.back().type != 3)
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log_error("Parser error in function expr `%s'.\n", orig_expr);
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return stack.back().sig;
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}
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struct LibertyFrontend : public Frontend {
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LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read_liberty [filename]\n");
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log("\n");
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log("Read cells from liberty file as modules into current design.\n");
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log("\n");
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log(" -lib\n");
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log(" only create empty blackbox modules\n");
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log("\n");
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log(" -ignore_redef\n");
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message.)\n");
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log("\n");
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log(" -setattr <attribute_name>\n");
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log(" set the specified attribute (to the value 1) on all loaded modules\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_lib = false;
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bool flag_ignore_redef = false;
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std::vector<std::string> attributes;
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log_header("Executing Liberty frontend.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-lib") {
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flag_lib = true;
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continue;
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}
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if (arg == "-ignore_redef") {
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flag_ignore_redef = true;
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continue;
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}
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if (arg == "-setattr" && argidx+1 < args.size()) {
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attributes.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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LibertyParser parser(f);
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int cell_count = 0;
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for (auto cell : parser.ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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std::string cell_name = RTLIL::escape_id(cell->args.at(0));
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if (design->modules.count(cell_name)) {
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if (flag_ignore_redef)
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continue;
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log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
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}
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if (!flag_lib)
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{
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LibertyAst *ff = cell->find("ff");
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if (ff != NULL) {
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log("Warning: skipping flip-flop cell %s.\n", RTLIL::id2cstr(cell_name));
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continue;
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}
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LibertyAst *latch = cell->find("latch");
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if (latch != NULL) {
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log("Warning: skipping latch cell %s.\n", RTLIL::id2cstr(cell_name));
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continue;
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}
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}
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// log("Processing cell type %s.\n", RTLIL::id2cstr(cell_name));
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cell_count++;
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RTLIL::Module *module = new RTLIL::Module;
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module->name = cell_name;
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design->modules[module->name] = module;
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for (auto &attr : attributes)
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module->attributes[attr] = 1;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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LibertyAst *dir = pin->find("direction");
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if (dir == NULL || dir->value == "internal")
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continue;
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log_assert(dir->value == "input" || dir->value == "output");
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = RTLIL::escape_id(pin->args.at(0));
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module->add(wire);
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if (dir->value == "input") {
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wire->port_input = true;
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continue;
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}
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wire->port_output = true;
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if (flag_lib)
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continue;
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LibertyAst *func = pin->find("function");
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if (func == NULL)
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log_error("Missing function on output %s of cell %s.\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name));
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RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
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module->connections.push_back(RTLIL::SigSig(wire, out_sig));
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continue;
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}
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module->fixup_ports();
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}
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log("Imported %d cell types from liberty file.\n", cell_count);
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}
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} LibertyFrontend;
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