riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution 

(Oreilly 'Flex & Bison' page 189)
This commit is contained in:
Udi Finkelstein 2017-09-30 06:39:07 +03:00
parent c5b204d8d2
commit 72a08eca3d
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
frontends/verilog/verilog_parser.y
View File

@ -142,7 +142,9 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%define parse.error verbose
%define parse.lac full
%expect 2
%nonassoc FAKE_THEN
%nonassoc TOK_ELSE
%debug
%%
@ -1261,7 +1263,7 @@ optional_else:
ast_stack.back()->children.push_back(cond);
ast_stack.push_back(block);
} behavioral_stmt |
/* empty */;
/* empty */ %prec FAKE_THEN;
case_body:
case_body case_item |
@ -1432,7 +1434,7 @@ gen_stmt_or_null:
gen_stmt_block | ';';
opt_gen_else:
TOK_ELSE gen_stmt_or_null | /* empty */;
TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
expr:
basic_expr {