mirror of https://github.com/YosysHQ/yosys.git
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()
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cd3e1095b0
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@ -379,7 +379,7 @@ struct AST_INTERNAL::ProcessGenerator
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// e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
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// function is called to clean up the first two assignments as they are overwritten by
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// the third assignment.
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void removeSignalFromCaseTree(const std::set<RTLIL::SigBit> &pattern, RTLIL::CaseRule *cs)
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void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
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{
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for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
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it->first.remove2(pattern, &it->second);
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@ -434,7 +434,7 @@ struct AST_INTERNAL::ProcessGenerator
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subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
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}
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removeSignalFromCaseTree(lvalue.to_sigbit_set(), current_case);
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removeSignalFromCaseTree(lvalue, current_case);
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remove_unwanted_lvalue_bits(lvalue, rvalue);
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current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
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}
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@ -511,7 +511,7 @@ struct AST_INTERNAL::ProcessGenerator
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subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
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this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
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removeSignalFromCaseTree(this_case_eq_lvalue.to_sigbit_set(), current_case);
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removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
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addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
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}
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break;
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