mirror of https://github.com/YosysHQ/yosys.git
rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)
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5462399c88
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@ -2659,8 +2659,35 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other
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void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
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{
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pool<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_pool();
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remove2(pattern_bits, other);
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if (other)
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cover("kernel.rtlil.sigspec.remove_other");
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else
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cover("kernel.rtlil.sigspec.remove");
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unpack();
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if (other != NULL) {
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log_assert(width_ == other->width_);
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other->unpack();
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}
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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if (bits_[i].wire == NULL) continue;
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for (auto &pattern_chunk : pattern.chunks()) {
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if (bits_[i].wire == pattern_chunk.wire &&
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bits_[i].offset >= pattern_chunk.offset &&
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bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
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bits_.erase(bits_.begin() + i);
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width_--;
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if (other != NULL) {
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other->bits_.erase(other->bits_.begin() + i);
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other->width_--;
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}
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}
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}
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}
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check();
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}
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void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
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