mirror of https://github.com/YosysHQ/yosys.git
Added AstNode::asInt()
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490d7a5bf2
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085c8e873d
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@ -792,9 +792,30 @@ int AstNode::isConst()
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return 0;
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}
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uint64_t AstNode::asInt(bool is_signed)
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{
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if (type == AST_CONSTANT)
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{
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RTLIL::Const v = bitsAsConst(64, is_signed);
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uint64_t ret = 0;
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for (int i = 0; i < 64; i++)
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if (v.bits.at(i) == RTLIL::State::S1)
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ret |= uint64_t(1) << i;
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return ret;
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}
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if (type == AST_REALVALUE)
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return realvalue;
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log_abort();
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}
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double AstNode::asReal(bool is_signed)
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{
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if (type == AST_CONSTANT) {
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if (type == AST_CONSTANT)
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{
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RTLIL::Const val(bits);
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bool is_negative = is_signed && val.bits.back() == RTLIL::State::S1;
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@ -247,6 +247,7 @@ namespace AST
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RTLIL::Const bitsAsConst(int width = -1);
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RTLIL::Const asAttrConst();
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RTLIL::Const asParaConst();
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uint64_t asInt(bool is_signed);
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bool bits_only_01();
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bool asBool();
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@ -30,7 +30,7 @@ AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname,
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if (argtypes[i] == "real" || argtypes[i] == "shortreal")
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log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
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else
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log(" arg %d (%s): %d\n", i, argtypes[i].c_str(), args[i]->bitsAsConst().as_int());
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log(" arg %d (%s): %lld\n", i, argtypes[i].c_str(), (long long)args[i]->asInt(args[i]->is_signed));
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if (rtype == "real" || rtype == "shortreal") {
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newNode = new AstNode(AST_REALVALUE);
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