mirror of https://github.com/YosysHQ/yosys.git
Bugfix in "read_verilog -D NAME=VAL" handling
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@ -303,10 +303,10 @@ struct VerilogFrontend : public Frontend {
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}
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if (arg == "-D" && argidx+1 < args.size()) {
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std::string name = args[++argidx], value;
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size_t equal = name.find('=', 2);
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size_t equal = name.find('=');
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if (equal != std::string::npos) {
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value = arg.substr(equal+1);
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name = arg.substr(0, equal);
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value = name.substr(equal+1);
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name = name.substr(0, equal);
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}
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defines_map[name] = value;
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continue;
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