Bugfix in "read_verilog -D NAME=VAL" handling

This commit is contained in:
Clifford Wolf 2016-11-28 14:45:05 +01:00
parent c17d98f55c
commit c7f6fb6e17
1 changed files with 3 additions and 3 deletions

View File

@ -303,10 +303,10 @@ struct VerilogFrontend : public Frontend {
}
if (arg == "-D" && argidx+1 < args.size()) {
std::string name = args[++argidx], value;
size_t equal = name.find('=', 2);
size_t equal = name.find('=');
if (equal != std::string::npos) {
value = arg.substr(equal+1);
name = arg.substr(0, equal);
value = name.substr(equal+1);
name = name.substr(0, equal);
}
defines_map[name] = value;
continue;