mirror of https://github.com/YosysHQ/yosys.git
Ignore celldefine directive in verilog front-end
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@ -116,6 +116,9 @@ YOSYS_NAMESPACE_END
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"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
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"`celldefine"[^\n]* /* ignore `celldefine */
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"`endcelldefine"[^\n]* /* ignore `endcelldefine */
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"`default_nettype"[ \t]+[^ \t\r\n/]+ {
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char *p = yytext;
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while (*p != 0 && *p != ' ' && *p != '\t') p++;
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