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Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values

This commit is contained in:
Clifford Wolf 2013-04-13 21:19:10 +02:00
parent c6198ea5a8
commit e0c408cb4a
2 changed files with 23 additions and 4 deletions
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8
frontends/ast/genrtlil.cc
View File

@ -337,9 +337,9 @@ struct AST_INTERNAL::ProcessGenerator
reg.sort_and_unify();
}
// remove all assignments to the given signal pattern in a case and all its children
// when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
// function is acalled to clean up the first two assignments as they are overwritten by
// remove all assignments to the given signal pattern in a case and all its children.
// e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
// function is called to clean up the first two assignments as they are overwritten by
// the third assignment.
void removeSignalFromCaseTree(RTLIL::SigSpec pattern, RTLIL::CaseRule *cs)
{
@ -461,7 +461,7 @@ struct AST_INTERNAL::ProcessGenerator
} else if (node->type == AST_BLOCK) {
processAst(node);
} else if (!generated_default_case)
current_case->compare.push_back(node->genWidthRTLIL(sw->signal.width));
current_case->compare.push_back(node->genWidthRTLIL(sw->signal.width, &subst_rvalue_from, &subst_rvalue_to));
}
sw->cases.push_back(current_case);
current_case = backup_case;

19
tests/simple/process.v
View File

@ -1,4 +1,23 @@
module blocking_cond (in, out);
input in;
output reg out;
reg tmp;
always @* begin
tmp = 1;
out = 1'b0;
case (1'b1)
tmp: out = in;
endcase
tmp = 0;
end
endmodule
// -------------------------------------------------------------
module uut(clk, arst, a, b, c, d, e, f, out1);
input clk, arst, a, b, c, d, e, f;