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Only allow posedge/negedge with 1 bit wide signals

This commit is contained in:
Clifford Wolf 2016-08-10 19:32:11 +02:00
parent 73b7232ec8
commit e9fe57c75e
1 changed files with 2 additions and 0 deletions
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2
frontends/ast/genrtlil.cc
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@ -241,6 +241,8 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
syncrule->signal = child->children[0]->genRTLIL();
if (GetSize(syncrule->signal) != 1)
log_error("Found posedge/negedge event on a signal that is not 1 bit wide at %s:%d!\n", always->filename.c_str(), always->linenum);
addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
proc->syncs.push_back(syncrule);
}