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Allow $size and $bits in verilog mode, actually check test case

This commit is contained in:
Clifford Wolf 2017-09-29 11:56:43 +02:00
parent 637a02eb5c
commit dbfd8460a9
3 changed files with 3 additions and 1 deletions
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2
frontends/ast/simplify.cc
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@ -1870,7 +1870,7 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
if (VERILOG_FRONTEND::sv_mode && (str == "\\$size" || str == "\\$bits"))
if (str == "\\$size" || str == "\\$bits")
{
if (str == "\\$bits" && children.size() != 1)
log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",

0
tests/simple/functions01.sv → tests/sat/sizebits.sv
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2
tests/sat/sizebits.ys Normal file
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@ -0,0 +1,2 @@
read_verilog -sv sizebits.sv
prep; sat -verify -prove-asserts