mirror of https://github.com/YosysHQ/yosys.git
Fixed bug with memories that do not have a down-to-zero data width
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cad40fc874
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450f6f59b4
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@ -883,11 +883,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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int mem_width, mem_size, addr_bits;
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id2ast->meminfo(mem_width, mem_size, addr_bits);
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int data_range_left = id2ast->children[0]->range_left;
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int data_range_right = id2ast->children[0]->range_right;
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std::stringstream sstr;
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sstr << "$mem2bits$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
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sstr << "$mem2bits$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
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std::string wire_id = sstr.str();
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AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
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AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
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wire->str = wire_id;
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if (current_block)
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wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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@ -1491,6 +1494,10 @@ skip_dynamic_range_lvalue_expansion:;
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int mem_width, mem_size, addr_bits;
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children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);
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int data_range_left = children[0]->id2ast->children[0]->range_left;
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int data_range_right = children[0]->id2ast->children[0]->range_right;
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int mem_data_range_offset = std::min(data_range_left, data_range_right);
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int addr_width_hint = -1;
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bool addr_sign_hint = true;
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children[0]->children[0]->children[0]->detectSignWidthWorker(addr_width_hint, addr_sign_hint);
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@ -1553,6 +1560,7 @@ skip_dynamic_range_lvalue_expansion:;
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{
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int offset = children[0]->children[1]->range_right;
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int width = children[0]->children[1]->range_left - offset + 1;
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offset -= mem_data_range_offset;
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std::vector<RTLIL::State> padding_x(offset, RTLIL::State::Sx);
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@ -1574,6 +1582,9 @@ skip_dynamic_range_lvalue_expansion:;
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AstNode *right_at_zero_ast = the_range->children.size() >= 2 ? the_range->children[1]->clone() : left_at_zero_ast->clone();
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AstNode *offset_ast = right_at_zero_ast->clone();
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if (mem_data_range_offset)
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offset_ast = new AstNode(AST_SUB, offset_ast, mkconst_int(mem_data_range_offset, true));
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while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
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while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
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if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
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@ -277,3 +277,33 @@ module memtest12 (
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{ram[adr], q} <= {din, ram[adr]};
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endmodule
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// ----------------------------------------------------------
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module memtest13 (
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input clk, rst,
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input [1:0] a1, a2, a3, a4, a5, a6,
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input [3:0] off1, off2,
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input [31:5] din1,
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input [3:0] din2, din3,
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output reg [3:0] dout1, dout2,
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output reg [31:5] dout3
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);
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reg [31:5] mem [0:3];
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always @(posedge clk) begin
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if (rst) begin
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mem[0] <= 0;
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mem[1] <= 0;
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mem[2] <= 0;
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mem[3] <= 0;
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end else begin
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mem[a1] <= din1;
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mem[a2][14:11] <= din2;
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mem[a3][5 + off1 +: 4] <= din3;
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dout1 <= mem[a4][12:9];
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dout2 <= mem[a5][5 + off2 +: 4];
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dout3 <= mem[a6];
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end
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end
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endmodule
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