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Added SV "restrict" keyword

This commit is contained in:
Clifford Wolf 2016-08-24 15:30:08 +02:00
parent 6523023645
commit cd18235f30
1 changed files with 2 additions and 1 deletions
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3
frontends/verilog/verilog_lexer.l
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@ -177,7 +177,8 @@ YOSYS_NAMESPACE_END
"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"predict" { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
"restrict" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"predict" { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }