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Bugfix in verilog_defaults argument parser

This commit is contained in:
Clifford Wolf 2017-12-24 17:21:37 +01:00
parent b66d50e62d
commit 34005348b6
1 changed files with 1 additions and 1 deletions
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2
frontends/verilog/verilog_frontend.cc
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@ -407,7 +407,7 @@ struct VerilogDefaults : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design*)
{
if (args.size() == 0)
if (args.size() < 2)
cmd_error(args, 1, "Missing argument.");
if (args[1] == "-add") {