diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 19fc3c6af..e5917b97e 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -407,7 +407,7 @@ struct VerilogDefaults : public Pass { } virtual void execute(std::vector args, RTLIL::Design*) { - if (args.size() == 0) + if (args.size() < 2) cmd_error(args, 1, "Missing argument."); if (args[1] == "-add") {