Fixed Verilog parser fix and more similar improvements

This commit is contained in:
Clifford Wolf 2016-03-15 12:22:31 +01:00
parent 81d4e9e7c1
commit 33c10350b2
1 changed files with 9 additions and 18 deletions

View File

@ -246,11 +246,10 @@ module_para_opt:
'#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
module_para_list:
single_module_para |
single_module_para ',' module_para_list |
/* empty */;
single_module_para | module_para_list ',' single_module_para;
single_module_para:
/* empty */ |
TOK_PARAMETER {
if (astbuf1) delete astbuf1;
astbuf1 = new AstNode(AST_PARAMETER);
@ -801,14 +800,14 @@ single_cell:
astbuf2->str = *$1;
delete $1;
ast_stack.back()->children.push_back(astbuf2);
} '(' cell_port_list_opt ')' |
} '(' cell_port_list ')' |
TOK_ID non_opt_range {
astbuf2 = astbuf1->clone();
if (astbuf2->type != AST_PRIMITIVE)
astbuf2->str = *$1;
delete $1;
ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
} '(' cell_port_list_opt ')';
} '(' cell_port_list ')';
prim_list:
single_prim |
@ -819,16 +818,16 @@ single_prim:
/* no name */ {
astbuf2 = astbuf1->clone();
ast_stack.back()->children.push_back(astbuf2);
} '(' cell_port_list_opt ')';
} '(' cell_port_list ')';
cell_parameter_list_opt:
'#' '(' cell_parameter_list ')' | /* empty */;
cell_parameter_list:
/* empty */ | cell_parameter |
cell_parameter ',' cell_parameter_list;
cell_parameter | cell_parameter_list ',' cell_parameter;
cell_parameter:
/* empty */ |
expr {
AstNode *node = new AstNode(AST_PARASET);
astbuf1->children.push_back(node);
@ -842,19 +841,11 @@ cell_parameter:
delete $2;
};
cell_port_list_opt:
/* empty */ |
cell_port_list |
/* empty */ ',' {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
} cell_port_list;
cell_port_list:
cell_port |
cell_port_list ',' cell_port;
cell_port | cell_port_list ',' cell_port;
cell_port:
/* empty */ |
expr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);