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made the generate..endgenrate keywords optional

This commit is contained in:
Clifford Wolf 2014-06-06 23:05:01 +02:00
parent 76da2fe172
commit 5281562d0e
1 changed files with 8 additions and 4 deletions
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12
frontends/verilog/parser.y
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@ -373,6 +373,8 @@ range_or_integer:
module_body:
module_body module_body_stmt |
/* the following line makes the generate..endgenrate keywords optional */
module_body gen_stmt |
/* empty */;
module_body_stmt:
@ -1013,9 +1015,12 @@ single_arg:
};
module_gen_body:
module_gen_body gen_stmt |
module_gen_body gen_stmt_or_module_body_stmt |
/* empty */;
gen_stmt_or_module_body_stmt:
gen_stmt | module_body_stmt;
// this production creates the obligatory if-else shift/reduce conflict
gen_stmt:
TOK_FOR '(' {
@ -1054,15 +1059,14 @@ gen_stmt:
if ($6 != NULL)
delete $6;
ast_stack.pop_back();
} |
module_body_stmt;
};
gen_stmt_block:
{
AstNode *node = new AstNode(AST_GENBLOCK);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} gen_stmt {
} gen_stmt_or_module_body_stmt {
ast_stack.pop_back();
};