mirror of https://github.com/YosysHQ/yosys.git
Added read_verilog -icells option
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@ -46,7 +46,7 @@ namespace AST {
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// instanciate global variables (private API)
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namespace AST_INTERNAL {
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bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
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bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
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AstNode *current_ast, *current_ast_mod;
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std::map<std::string, AstNode*> current_scope;
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RTLIL::SigSpec *genRTLIL_subst_from = NULL;
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@ -826,11 +826,12 @@ static AstModule* process_module(AstNode *ast)
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current_module->mem2reg = flag_mem2reg;
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current_module->lib = flag_lib;
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current_module->noopt = flag_noopt;
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current_module->icells = flag_icells;
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return current_module;
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}
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// create AstModule instances for all modules in the AST tree and add them to 'design'
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool ignore_redef)
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef)
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{
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current_ast = ast;
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flag_dump_ast1 = dump_ast1;
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@ -841,6 +842,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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flag_mem2reg = mem2reg;
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flag_lib = lib;
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flag_noopt = noopt;
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flag_icells = icells;
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assert(current_ast->type == AST_DESIGN);
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for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
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@ -877,6 +879,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
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flag_mem2reg = mem2reg;
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flag_lib = lib;
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flag_noopt = noopt;
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flag_icells = icells;
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use_internal_line_num();
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std::string para_info;
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@ -959,6 +962,7 @@ RTLIL::Module *AstModule::clone() const
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new_mod->mem2reg = mem2reg;
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new_mod->lib = lib;
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new_mod->noopt = noopt;
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new_mod->icells = icells;
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return new_mod;
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}
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@ -231,13 +231,13 @@ namespace AST
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};
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// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool ignore_redef = false);
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool icells = false, bool ignore_redef = false);
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// parametric modules are supported directly by the AST library
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// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
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struct AstModule : RTLIL::Module {
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AstNode *ast;
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bool nolatches, nomem2reg, mem2reg, lib, noopt;
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bool nolatches, nomem2reg, mem2reg, lib, noopt, icells;
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virtual ~AstModule();
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virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
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virtual RTLIL::Module *clone() const;
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@ -258,7 +258,7 @@ namespace AST
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namespace AST_INTERNAL
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{
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// internal state variables
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extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
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extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
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extern AST::AstNode *current_ast, *current_ast_mod;
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extern std::map<std::string, AST::AstNode*> current_scope;
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extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial;
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@ -1334,6 +1334,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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AstNode *child = *it;
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if (child->type == AST_CELLTYPE) {
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cell->type = child->str;
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if (flag_icells && cell->type.substr(0, 2) == "\\$")
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cell->type = cell->type.substr(1);
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continue;
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}
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if (child->type == AST_PARASET) {
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@ -99,6 +99,9 @@ struct VerilogFrontend : public Frontend {
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log(" don't perform basic optimizations (such as const folding) in the\n");
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log(" high-level front-end.\n");
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log("\n");
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log(" -icells\n");
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log(" interpret cell types starting with '$' as internal cell types\n");
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log("\n");
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log(" -ignore_redef\n");
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message.)\n");
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@ -127,6 +130,7 @@ struct VerilogFrontend : public Frontend {
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bool flag_nopp = false;
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bool flag_lib = false;
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bool flag_noopt = false;
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bool flag_icells = false;
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bool flag_ignore_redef = false;
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std::map<std::string, std::string> defines_map;
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std::list<std::string> include_dirs;
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@ -183,6 +187,10 @@ struct VerilogFrontend : public Frontend {
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flag_noopt = true;
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continue;
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}
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if (arg == "-icells") {
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flag_icells = true;
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continue;
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}
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if (arg == "-ignore_redef") {
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flag_ignore_redef = true;
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continue;
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@ -228,7 +236,7 @@ struct VerilogFrontend : public Frontend {
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frontend_verilog_yyparse();
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frontend_verilog_yylex_destroy();
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_ignore_redef);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef);
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if (!flag_nopp)
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fclose(fp);
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