mirror of https://github.com/YosysHQ/yosys.git
Implemented basic real arithmetic
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9dd16fa41c
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442a8e2875
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@ -32,7 +32,7 @@
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#include <sstream>
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#include <stdarg.h>
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#include <assert.h>
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#include <math.h>
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using namespace AST;
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using namespace AST_INTERNAL;
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@ -760,6 +760,35 @@ bool AstNode::asBool()
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return false;
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}
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int AstNode::isConst()
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{
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if (type == AST_CONSTANT)
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return 1;
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if (type == AST_REALVALUE)
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return 2;
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return 0;
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}
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double AstNode::asReal(bool is_signed)
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{
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if (type == AST_CONSTANT) {
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RTLIL::Const val;
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val.bits = bits;
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double p = exp2(val.bits.size()-32);
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if (val.bits.size() > 32)
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val.bits.erase(val.bits.begin(), val.bits.begin()+(val.bits.size()-32));
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int32_t v = val.as_int() << (32-val.bits.size());
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if (is_signed)
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return v * p;
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return uint32_t(v) * p;
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}
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if (type == AST_REALVALUE)
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return realvalue;
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return 0;
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}
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// create a new AstModule from an AST_MODULE AST node
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static AstModule* process_module(AstNode *ast, bool defer)
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{
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@ -240,6 +240,10 @@ namespace AST
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RTLIL::Const asAttrConst();
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RTLIL::Const asParaConst();
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bool asBool();
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// helper functions for real valued const eval
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int isConst(); // return '1' for AST_CONSTANT and '2' for AST_REALVALUE
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double asReal(bool is_signed);
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};
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// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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@ -32,7 +32,7 @@
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#include <sstream>
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#include <stdarg.h>
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#include <assert.h>
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#include <math.h>
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using namespace AST;
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using namespace AST_INTERNAL;
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@ -1433,10 +1433,22 @@ skip_dynamic_range_lvalue_expansion:;
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if (0) { case AST_MUL: const_func = RTLIL::const_mul; }
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if (0) { case AST_DIV: const_func = RTLIL::const_div; }
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if (0) { case AST_MOD: const_func = RTLIL::const_mod; }
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if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
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RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
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children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
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newNode = mkconst_bits(y.bits, sign_hint);
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if (children[0]->isConst() && children[1]->isConst()) {
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if (children[0]->isConst() + children[1]->isConst() > 2) {
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newNode = new AstNode(AST_REALVALUE);
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switch (type) {
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case AST_ADD: newNode->realvalue = children[0]->asReal(sign_hint) + children[1]->asReal(sign_hint); break;
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case AST_SUB: newNode->realvalue = children[0]->asReal(sign_hint) - children[1]->asReal(sign_hint); break;
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case AST_MUL: newNode->realvalue = children[0]->asReal(sign_hint) * children[1]->asReal(sign_hint); break;
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case AST_DIV: newNode->realvalue = children[0]->asReal(sign_hint) / children[1]->asReal(sign_hint); break;
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case AST_MOD: newNode->realvalue = fmod(children[0]->asReal(sign_hint), children[1]->asReal(sign_hint)); break;
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default: log_abort();
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}
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} else {
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RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
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children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
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newNode = mkconst_bits(y.bits, sign_hint);
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}
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}
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break;
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if (0) { case AST_POS: const_func = RTLIL::const_pos; }
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