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Fixed handling of different signedness in power operands

This commit is contained in:
Clifford Wolf 2013-11-08 11:06:11 +01:00
parent b04051a0e2
commit 9f49d538e1
1 changed files with 1 additions and 1 deletions
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2
frontends/ast/simplify.cc
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@ -1020,7 +1020,7 @@ skip_dynamic_range_lvalue_expansion:;
if (0) { case AST_POW: const_func = RTLIL::const_pow; }
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? sign_hint : false, width_hint);
RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint);
newNode = mkconst_bits(y.bits, sign_hint);
}
break;