mirror of https://github.com/YosysHQ/yosys.git
Improved parsing of large integer constants
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48dc6ab98d
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@ -52,6 +52,8 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
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carry = digits[i] % 2;
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digits[i] /= 2;
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}
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while (!digits.empty() && !digits.front())
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digits.erase(digits.begin());
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return carry;
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}
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@ -90,10 +92,15 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
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if (base == 10) {
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data.clear();
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if (len_in_bits < 0)
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len_in_bits = ceil(digits.size()/log10(2));
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for (int i = 0; i < len_in_bits; i++)
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data.push_back(my_decimal_div_by_two(digits) ? RTLIL::S1 : RTLIL::S0);
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if (len_in_bits < 0) {
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while (!digits.empty())
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data.push_back(my_decimal_div_by_two(digits) ? RTLIL::S1 : RTLIL::S0);
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while (data.size() < 32)
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data.push_back(RTLIL::S0);
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} else {
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for (int i = 0; i < len_in_bits; i++)
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data.push_back(my_decimal_div_by_two(digits) ? RTLIL::S1 : RTLIL::S0);
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}
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return;
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}
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@ -151,20 +158,24 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
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str = code.c_str();
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char *endptr;
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long intval = strtol(str, &endptr, 10);
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long len_in_bits = strtol(str, &endptr, 10);
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// Simple base-10 integer
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if (*endptr == 0) {
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std::vector<RTLIL::State> data;
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my_strtobin(data, str, -1, 10, case_type);
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if (data.back() == RTLIL::S1)
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data.push_back(RTLIL::S0);
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return AstNode::mkconst_bits(data, true);
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}
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// Simple 32 bit integer
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if (*endptr == 0)
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return AstNode::mkconst_int(intval, true);
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// unsized constant
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if (str == endptr)
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intval = -1;
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len_in_bits = -1;
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// The "<bits>'s?[bodh]<digits>" syntax
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if (*endptr == '\'')
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{
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int len_in_bits = intval;
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std::vector<RTLIL::State> data;
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bool is_signed = false;
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if (*(endptr+1) == 's') {
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@ -188,6 +199,12 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
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default:
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return NULL;
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}
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if (len_in_bits < 0) {
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if (is_signed && data.back() == RTLIL::S1)
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data.push_back(RTLIL::S0);
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while (data.size() < 32)
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data.push_back(RTLIL::S0);
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}
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return AstNode::mkconst_bits(data, is_signed);
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}
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