mirror of https://github.com/YosysHQ/yosys.git
Copy Verific vdbs files to Yosys "share" data directory
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2
Makefile
2
Makefile
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@ -92,7 +92,7 @@ endif
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ifeq ($(ENABLE_VERIFIC),1)
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VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
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VERIFIC_COMPONENTS ?= verilog vhdl database util containers
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CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -D'VERIFIC_DIR="$(VERIFIC_DIR)"'
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CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
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LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS))
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endif
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@ -1 +1,16 @@
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OBJS += frontends/verific/verific.o
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ifeq ($(ENABLE_VERIFIC),1)
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EXTRA_TARGETS += share/verific
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share/verific:
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rm -rf share/verific.new
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mkdir -p share/verific.new
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cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs share/verific.new/vhdl_vdbs_1993
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cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008 share/verific.new/vhdl_vdbs_2008
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mv share/verific.new share/verific
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endif
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@ -27,7 +27,7 @@
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#include <string.h>
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#include <dirent.h>
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#ifdef VERIFIC_DIR
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#ifdef YOSYS_ENABLE_VERIFIC
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#include "veri_file.h"
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#include "vhdl_file.h"
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@ -482,7 +482,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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}
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}
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#endif /* VERIFIC_DIR */
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#endif /* YOSYS_ENABLE_VERIFIC */
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struct VerificPass : public Pass {
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VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
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@ -509,7 +509,7 @@ struct VerificPass : public Pass {
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log("Visit http://verific.com/ for more information on Verific.\n");
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log("\n");
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}
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#ifdef VERIFIC_DIR
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#ifdef YOSYS_ENABLE_VERIFIC
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n");
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@ -553,7 +553,7 @@ struct VerificPass : public Pass {
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}
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if (args.size() > 1 && args[1] == "-vhdl87") {
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vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
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vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
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for (size_t argidx = 2; argidx < args.size(); argidx++)
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if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87))
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log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
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@ -561,7 +561,7 @@ struct VerificPass : public Pass {
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}
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if (args.size() > 1 && args[1] == "-vhdl93") {
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vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
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vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
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for (size_t argidx = 2; argidx < args.size(); argidx++)
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if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93))
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log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
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@ -569,7 +569,7 @@ struct VerificPass : public Pass {
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}
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if (args.size() > 1 && args[1] == "-vhdl2k") {
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vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
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vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
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for (size_t argidx = 2; argidx < args.size(); argidx++)
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if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K))
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log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
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@ -577,7 +577,7 @@ struct VerificPass : public Pass {
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}
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if (args.size() > 1 && args[1] == "-vhdl2008") {
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vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
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vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
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for (size_t argidx = 2; argidx < args.size(); argidx++)
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if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008))
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log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
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@ -617,7 +617,7 @@ struct VerificPass : public Pass {
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log_cmd_error("Missing or unsupported mode parameter.\n");
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}
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#else /* VERIFIC_DIR */
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#else /* YOSYS_ENABLE_VERIFIC */
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virtual void execute(std::vector<std::string>, RTLIL::Design *) {
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log_cmd_error("This version of Yosys is built without Verific support.\n");
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}
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