mirror of https://github.com/YosysHQ/yosys.git
Fixed mapping of Verific WIDE_DFFRS operator
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@ -466,9 +466,9 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
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if (inst->Type() == OPER_WIDE_DFFRS) {
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RTLIL::SigSpec sig_set = operatorInport(inst, "set", net_map);
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RTLIL::SigSpec sig_reset = operatorInport(inst, "reset", net_map);
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if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_set.is_fully_const() && !sig_set.as_bool()) {
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if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool())
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module->addDff(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), IN, OUT);
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} else
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else
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module->addDffsr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), sig_set, sig_reset, IN, OUT);
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return true;
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}
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