mirror of https://github.com/YosysHQ/yosys.git
Added $bits() for memories as well.
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17f8b41605
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2dea42e903
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@ -1870,19 +1870,43 @@ skip_dynamic_range_lvalue_expansion:;
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goto apply_newNode;
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}
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if (str == "\\$size")
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if (str == "\\$size" || str == "\\$bits")
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{
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if (children.size() != 1)
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log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
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RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
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AstNode *buf = children[0]->clone();
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int mem_depth = 1;
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AstNode *id_ast = NULL;
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// Is this needed?
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//while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
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buf->detectSignWidth(width_hint, sign_hint);
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if (str == "\\$bits") {
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if (buf->type == AST_IDENTIFIER) {
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id_ast = buf->id2ast;
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if (id_ast == NULL && current_scope.count(buf->str))
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id_ast = current_scope.at(buf->str);
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if (!id_ast)
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log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
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if (id_ast->type == AST_MEMORY) {
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AstNode *mem_range = id_ast->children[1];
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if (mem_range->type == AST_RANGE) {
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if (!mem_range->range_valid)
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log_error("Failed to detect width of memory access `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
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mem_depth = mem_range->range_left - mem_range->range_right + 1;
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} else if (mem_range->type == AST_MULTIRANGE) {
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for (auto n : mem_range->children)
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mem_depth *= (n->range_left - n->range_right + 1);
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} else
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log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
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}
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}
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}
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delete buf;
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newNode = mkconst_int(width_hint, false);
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newNode = mkconst_int(width_hint * mem_depth, false);
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goto apply_newNode;
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}
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@ -1,4 +1,5 @@
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module functions01;
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wire [3:0]x;
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wire [$size(x)-1:0]x_size;
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wire [$size({x, x})-1:0]xx_size;
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@ -7,11 +8,9 @@ wire [$size(y)-1:0]y_size;
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wire [3:0]z[0:5][0:7];
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wire [$size(z)-1:0]z_size;
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//
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// The following are not supported yet:
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//
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//wire [$bits(x)-1:0]x_bits;
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//wire [$bits({x, x})-1:0]xx_bits;
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wire [$bits(x)-1:0]x_bits;
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wire [$bits({x, x})-1:0]xx_bits;
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wire [$bits(y)-1:0]y_bits;
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wire [$bits(z)-1:0]z_bits;
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endmodule
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