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Bugfix in Verific front-end

This commit is contained in:
Clifford Wolf 2016-02-03 08:59:57 +01:00
parent 4a3e1ded1e
commit 6a27cbe5b1
1 changed files with 5 additions and 2 deletions
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7
frontends/verific/verific.cc
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@ -773,8 +773,11 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
}
IdString port_name_id = RTLIL::escape_id(port_name);
auto &sigvec = cell_port_conns[port_name_id];
if (GetSize(sigvec) <= port_offset)
sigvec.resize(port_offset+1, State::Sz);
if (GetSize(sigvec) <= port_offset) {
SigSpec zwires = module->addWire(NEW_ID, port_offset+1-GetSize(sigvec));
for (auto bit : zwires)
sigvec.push_back(bit);
}
sigvec[port_offset] = net_map.at(pr->GetNet());
}